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stc89cxx series mcu stc89lexx series mcu data sheet 1
contents chapter 1 introduction ......................................................................4 1.1 features ................................................................................................. 4 1.2 block diagram ...................................................................................... 5 1.3 pin configurations .............................................................................. 6 1.4 pin descriptions ................................................................................... 7 1.5 pin package drawings ......................................................................... 8 chapter 2 power managenment, reset ........................ 11 2.1 power management .......................................................................... 11 2.1.1 idle mode .....................................................................................................11 2.1.2 power down (pd) mode ............................................................................12 2.2 reset control .................................................................................. 16 2.2.1 reset pin ...................................................................................................... 16 2.2.2 power-on reset (por) .............................................................................. 17 2.2.3 watch-dog-timer .......................................................................................17 2.2.4 software reset .........................................................................................20 2.2.5 max810 power-on-reset delay ..................................................................20 chapter 3 memory organization ...................................................21 3.1 program memory ............................................................................... 21 3.2 data memory ...................................................................................... 22 3.2.1 on-chip scratch-pad ram .......................................................................22 3.2.2 auxiliary ram ...........................................................................................22 3.2.3 external ram .............................................................................................22 3.2.4 special function register for ram ..........................................................23 chapter 4 configurable i/o ports configurations ............................ 29 4.1 quasi-bidirectional i/o ....................................................................... 29 4.2 push-pull output ................................................................................. 30 4.3 input-only mode ................................................................................. 30 4.4 open-drain output ............................................................................. 30 chapter 5 instruction system .........................................................31 5.1 special function registers ................................................................ 31 5.2 addressing modes .............................................................................. 36 5.3 instruction set summary .................................................................. 37 5.4 instruction definitions ....................................................................... 41 2
chapter 6 interrupt .........................................................................78 6.1 interrupt structure ............................................................................ 79 6.2 interrupt register .............................................................................. 80 6.3 interrupt priorities ............................................................................ 84 6.4 how interrupts are handled ............................................................ 84 6.5 external interrupts ........................................................................... 85 6.6 response time ................................................................................... 88 chapter 7 timer/counter ................................................................89 7.1 timer/counter 0 mode of operation ............................................... 92 7.2 timer/counter 1 mode of operation ............................................... 9 5 7.3 timer/counter 2 mode of operation ............................................. 100 chapter 8 uart with enhanced function ...................................109 8.1 uart mode of operation ............................................................... 112 8.2 frame error detection .................................................................... 118 8.3 multiprocessor communications.................................................... 118 8.4 automatic address recognition ...................................................... 120 8.5 buad rates ........................................................................................ 122 chapter 9 iap / eeprom ............................................................123 9.1 iap / isp control register .............................................................. 123 9.2 stc89xx series internal eeprom selection table ..................... 125 9.3 iap/eeprom assembly language program introduction ........ 126 9.4 operating internal eeprom demo by assembly language ..... 128 appendix a: assembly language programming ........................132 appendix b: 8051 c programming ..............................................154 appendix c: stc89xx series selection table ..............................164 3
1.1 features enhanced 80c51 central processing unit ,6t or 12t per machine cycle operation voltage range: 5.5v~3.3v (stc89c series) or 2.0v~ 3.6v (stc89le series) operation frequency range: 0- 48mhz@12t, or 0-24mhz@6t on-chip 4/8/13/16/20/32/64k flash program memory with flexible isp/iap capability on-chip 1280 byte / 512 byte ram be capable of addressing up to 64k byte of external ram be capable of addressing up to 64k bytes external memory dual data pointer (dptr) to speed up data movement three 16-bit timer/counter, timer 2 is an up/down counter with programmable clcok output on p1.0 8 vector-address, 4 level priority interrupt capability one enhanced uart with hardware address-recognition, frame-error detection function, and with self baud- rate generator. one 15 bits watch-dog-timer with 8-bit pre-scaler (one-time-enabled) integrate max810 ? specialized reset circuit three power management modes: idle mode and power-down mode low emi: inhibit ale emission power down mode can be woken-up by int0/p3.2 pin, int1/p3.3 pin, t0/p3.4, t1/p3.5, rxd/p3.0 pin, int2/p4.3, int3/p4.2 maximum 39 programmable i/o ports are available four 8-bit bi-directonal ports; extra four-bit additional p4 are available for plcc-44 and lqfp-44 operating temperature: -40 ~ +85 o c (industrial) / 0~75 o c (commercial) package type : p qfp-44 ,lqfp-44 ,pdip-40,plcc-44 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chapter 1 introduction stc89xx series, which is produced by stc mcu limited, is a 8-bit single-chip microcontroller with a fully compatible instruction set with industrial-standard 80c51 series microcontroller. there is 64k bytes flash memory embeded for appliaction program, which is shared with in-system-programming code.in-system- programming (isp) and in-application-programming (iap) support the users to upgrade the program and data in system. isp allows the user to download new code without removing the microcontroller from the actual end product;iap means that the device can write non-valatile data in flash memory while the application program is running. there are 1280 bytes or 512 bytes on-chip ram embedded that provides requirement from wide field application. the user can configure the device to run in 12 clocks per machine cycle, and to get the same performance just as he uses another standard 80c51 device that is provided by other vendor, or 6 clocks per machine cycle to achieve twice performance. the stc89xx series retain all features of the standard 80c51. in addition, the stc89xx series have a extra i/o port (p4 ), timer 2, a 8-sources, 4-priority-level interrupt structure, on-chip crystal oscillator,and a one-time enabled watchdog timer. 4
1.2 block diagram the cpu kernel of stc89xx series are fully compatible to the standard 8051 microcontroller, maintains all instruction mnemonics and binary compatibility. stc89xx series can execute the fastest instructions per 6 clock cycles or 12 clock cycles(as the same as the standard 80c51) . improvement of individual programs depends on the actual instructions used. stc89xx block diagram 256 byte ram ram addr register flash 64k program counter b register acc tmp2 tmp1 stack poniter alu psw port 0,1,2,3,4 latch wdt control unit xtal2 xtal1 reset aux-ram 1024 byte isp/iap address generator timer 0/1 uart port 0,1,2,3,4 driver p0, p1,p2,p3,p4 psen timer 2 ale ea 5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vcc ale psen rst txd/p3.1 xtal2 xtal1 gnd wr/p3.6 rd/p3.7 rxd/p3.0 t0/p3.4 t1/p3.5 int1/p3.3 int0/p3.2 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ea p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 t2/p1.0 t2ex/p1.1 p1.2 p1.3 p1.4 p1.5 p1.7 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 rst txd/p3.1 rxd/p3.0 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 ale psen vcc xtal2 xtal1 gnd wr/p3.6 rd/p3.7 p0.4 p0.5 p0.6 ea p4.1 p2.7 p2.6 p2.5 p0.7 p1.5 p1.7 int2/p4.3 p1.4 p1.3 p1.2 t2ex/p1.1 t2/p1.0 p0.0 p0.1 p0.2 p0.3 int3/p4.2 p4.0 p2.0 p2.1 p2.2 p2.3 p2.4 pdip-40 35 i/o ports lqfp-44 39 i/o ports 1.3 pin configurations plcc-44 36 i/o ports 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ale psen p0.4 p0.5 p0.6 ea p4.1 p2.7 p2.6 p2.5 p0.7 xtal2 xtal1 gnd wr/p3.6 rd/p3.7 p4.0 p2.0 p2.1 p2.2 p2.3 p2.4 rst txd/p3.1 rxd/p3.0 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 p1.5 p1.7 int2/p4.3 vcc p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 p0.0 p0.1 p0.2 p0.3 p4.2/int3 p1.6 p1.6 p1.6 6 3 qfp-44
1.4 pin descriptions mnemonic qfp44 pdip40 plcc44 description p0.0 ~ p0.7 37~30 39~32 43~36 port0 :port0 is an 8-bit bi-directional i/o port with pull-up resistance. except being as gpio, port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. p1.0 ~ p1.7 40~44 1-8 2~9 port1 : general-purposed i/o with weak pull-up resistance inside. when 1s are written into port1, the strong output driving cmos only turn-on two period and then the weak pull-up resistance keep the port high. p1.0 is also used as one of event sources for timer2, or output carrier of timer 2, alias t2. p1.1 is also used as one of interrupt-controlling sources for time 2, alias t2ex. 1~3 p1.0/t2 40 1 2 p1.1/t2ex 41 2 3 p2.0 ~ p2.7 18-25 21-28 24~31 port2 : port2 is an 8-bit bi -directional i/o port with pull-up resistance. except being as gpio, port2 emits the high-order address byte during accessing to external program and data memory. p3.0/rxd 5 10 11 port3 : general-purposed i/o with weak pull-up resistance inside. when 1s are written into port1, the strong output driving cmos only turn-on two period and then the weak pull-up resistance keep the port high. port3 also serves the functions of various special features. p3.0 and p3.1 act as receiver and transceiver of the data for uart func- tion block, alias rxd and txd. p3.2 and p3.3 also act as external interrupt sources, alias /int0 and /int1. p3.4 and p3.5 also act as event sources for timer0 and timer1 individu- ally, alias t0 and t1. p3.6 also acts as write signal while access to external memory,alias /wr. p3.7 also acts as read signal while access to external memory, alias /rd. p3.1/txd 7 11 13 p3.2/int0 8 12 14 p3.3/int1 9 13 15 p3.4/t0 10 14 16 p3.5/t1 11 15 17 p3.6/wr 12 16 18 p3.7/rd 13 17 19 p4.0 17 23 port4 : port4 are extended i/o ports such like port1. it can be available only on lqfp-44, plcc-44. p4.2 and p4.3 also act as external interrupt sources, alias /int3 and /int2. p4.1 28 34 p4.2/int3 39 1 p4.3/int2 6 12 rst 4 9 10 reset : a high on this pin for at least two machine cycles will reset the device. /ea 29 31 35 ea must be kept at low to enable the device to fetch program code from external flash memory. an internal pull-up resistance has been embedded in this pin. /ale 27 30 33 output pulse for latching the low byte of address during accesses to external memory. /psen 26 29 32 the read strobe to external program memory, low active. xtal1 15 19 21 crystal 1: input to the inverting oscillator amplifier.receives the external oscillator signal when an external oscillator is used. xtal2 14 18 20 crystal 2: output from the inverting amplifier. this pin should be floated when an external oscillator is used. vcc 38 40 44 power gnd 16 20 22 ground 7
1.5 pin package drawings d1 d e1 e 1 11 12 22 23 33 44 34 a a2 c1 b e 0.05max 0 0.25 l l1 gate plane seating plane a1 symbols min. nom max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 c1 0.09 - 0.16 d 12.00 d1 10.00 e 12.00 e1 10.00 e 0.80 b(w/o plating) 0.25 0.30 0.35 l 0.45 0.60 0.75 l1 1.00ref 0 0 0 3.5 0 7 0 1 variations (all dimensions shown in mm notes: 1.jedec outline:ms-026 bsb 2.dimensions d1 and e1 d0 not include mold protrusion. allowble protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions imcluding mold mismatch. 3.dimension b does not include dambar protrusion.allowble dambar protrusion shall not cause the lead width to exceed the maximun b dimnsion by more than 0.08mm. lqfp-44 outline package 8
40 21 1 20 e1 d e c e 0 0.001tyb. 0.050tyb. a1 a2 a seating plane l 0.050tyb. h symbols min nor max a - - 0.190 a1 0.015 - - a2 0.015 0.155 0.160 c 0.008 - 0.015 d 2.025 2.060 2.070 e 0.600 e1 0.540 0.545 0.550 l 0.120 0.130 0.140 0.630 0.650 0.670 00715 note: 1.jedec outline :ms-011 ac e pdip-40 outline package 9
b a a2 a1 18 28 40 29 39 7 17 1 e he 6 d hd b1 gd l 0 ge seating plane y c h e symbols dimensions in inch dimensions in millmeters min nom max min nom max a 0.165 - 0.180 4.191 - 4.572 a1 0.020 - - 0.508 - - a2 0.147 - 0.158 3.734 - 4.013 b1 0.026 0.028 0.032 0.660 0.711 0.813 b 0.013 0.017 0.021 0.330 0.432 0.533 c 0.007 0.010 0.0013 0.178 0.254 0.330 d 0.650 0.653 0.656 16.510 16.586 16.662 e 0.650 0.653 0.656 16.510 16.586 16.662 0.050bsc 1.270bsc gd 0.590 0.610 0.630 14.986 15.494 16.002 ge 0.590 0.610 0.630 14.986 15.494 16.002 hd 0.685 0.690 0.695 17.399 17.526 17.653 he 0.685 0.690 0.695 17.399 17.526 17.653 l 0.100 - 0.112 2.540 - 2.845 y - - 0.004 - - 0.102 note: 1.jedec outline :m0-047 ac 2.datum plane h is lacated at the bottom of the mold parting line coincident with where the lead exits the body. 3.dimensions e and d d0 not include mode protrusion. allowable protrusion is 10 mil pre side.dimensions e and d d0 include mold mismatch and are determined at datum plane h . 4.dimension b1 does not include dambar protrusion. e plcc-44 outline package 10
2.1.1 idle mode an instruction that sets idl/pcon.0 causes that to be the last instruction executed before going into the idle mode, the internal clock is gated off to the cpu but not to the interrupt, timer, wdt and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. idle mode leaves the peripherals running in order to allow them to wake up the cpu when an interrupt is generated. timer 0, timer 1, timer 2 and uart will continue to function during idle mode. there are two ways to terminate the idle. activation of any enabled interrupt will cause idl/pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti, the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits (gfo and gf1) can be used to give art indication if an interrupt occurred during normal operation or during idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way to wake-up from idle is to pull reset high to generate internal hardware reset.since the clock oscillator is still running, the hardware reset neeeds to be held active for only two system clock cycles(24 system clock) to complete the reset. 2.1 power management there are two power saving modes, which are selectable to drive the stc89xx enter power-saving mode by set- ting the following sfr pcon. pcon register (power control register) lsb bit b7 b6 b5b4b3b2b1b0 name smod smod0 - pof gf1 gf0 pd idl smod : double baud rate of uart interface 0 keep normal baud rate when the uart is used in mode 1,2 or 3. (defaut) 1 double baud rate bit when the uart is used in mode 1,2 or 3. smod0 : sm0/fe bit select for scon.7; setting this bit will set scon.7 as frame error function. clearing it to set scon.7 as one bit of uart mode selection bits. b5 : reserved pof : power-on flag. it is set by power-off-on action and can only cleared by software. gf1 : general-purposed flag 1 gf0 : general-purposed flag 0 pd : power-down bit. idl : idle mode bit. chapter 2 power managenment, reset 11
2.1.2 power down (pd) mode an instruction that sets pd/pcon.1 cause that to be the last instruction executed before going into the power- down mode. in the power-down mode, the on-chip oscillator and the flash memory are stopped in order to minimize power consumption. only the power-on circuitry will continue to draw power during power-down. the contents of on-chip ram and sfrs are maintained. the only way to wake-up from power-down mode is hardware reset. the power-down mode can be woken-up by reset pin, external interrupt /int0~/int3, rxd pin, t0 pin, t1 pin . when it is woken-up by reset, the program will execute from the address 0x0000. be carefully to keep reset pin active for at least 10ms in order for a stable clock. if it is woken-up from i/o, the cpu will rework through jumping to related interrupt service routine. before the cpu rework, the clock is blocked and counted until 32768 in order for denouncing the unstable clock. to use i/o wake-up, interrupt-related registers have to be enabled and programmed accurately before power-down is entered. pay attention to have at least one ?nop? instruction subsequent to the power-down instruction if i/o wake-up is used. when terminating power-down by an interrupt, the wake up period is internally timed. at the negative edge on the interrupt pin, power-down is exited, the oscillator is restarted, and an internal timer begins counting. the internal clock will be allowed to propagate and the cpu will not resume execution until after the timer has reached internal counter full. after the timeout period, the interrupt service routine will begin. to prevent the interrupt from re-triggering, the interrupt service routine should disable the interrupt before returning. the interrupt pin should be held low until the device has timed out and begun executing. the user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 us until after one of the following conditions has occured: start of code execution(after any type of reset), or exit from power-down mode. the following example c program demostrates that power-down mode be woken-up by external interrupt . /*------------------------------------------------------------------*/ /* --- stc mcu international limited -------------------------------*/ /* --- stc89xx series mcu wake up power-down mode demo -----------------------*/ /* if you want to use the program or the program referenced in the */ /* article, please specify in which data and procedures from stc */ /*------------------------------------------------------------------*/ #include #include sbit begin_led = p1^2; //begin-led indicator indicates system start-up unsigned char is_power_down = 0; //set this bit before go into power-down mode sbit is_power_down_led_int0 = p1^7; //power-down wake-up led indicator on int0 sbit not_power_down_led_int0 = p1^6; //not power-down wake-up led indicator on int0 sbit is_power_down_led_int1 = p1^5; //power-down wake-up led indicator on int1 sbit not_power_down_led_int1 = p1^4; //not power-down wake-up led indicator on int1 sbit power_down_wakeup_pin_int0 = p3^2; //power-down wake-up pin on int0 sbit power_down_wakeup_pin_int1 = p3^3; //power-down wake-up pin on int1 sbit normal_work_flashing_led = p1^3; //normal work led indicator void normal_work_flashing (void); void int_system_init (void); void int0_routine (void); void int1_routine (void); 12
void main (void) { unsigned char j = 0; unsigned char wakeup_counter = 0; //clear interrupt wakeup counter variable wakeup_counter begin_led = 0; //system start-up led int_system_init ( ); //interrupt system initialization while(1) { p2 = wakeup_counter; wakeup_counter++; for(j=0; j<2; j++) { normal_work_flashing( ); //system normal work } is_power_down = 1; //set this bit before go into power-down mode pcon = 0x02; //after this instruction, mcu will be in power-down mode //external clock stop _nop_( ); _nop_( ); _nop_( ); _nop_( ); } } void int_system_init (void) { it0 = 0; /* external interrupt 0, low electrical level triggered */ // it0 = 1; /* external interrupt 0, negative edge triggered */ ex0 = 1; /* enable external interrupt 0 it1 = 0; /* external interrupt 1, low electrical level triggered */ // it1 = 1; /* external interrupt 1, negative edge triggered */ ex1 = 1; /* enable external interrupt 1 ea = 1; /* set global enable bit } void int0_routine (void) interrupt 0 { if (is_power_down) { //is_power_down ==1; /* power-down wakeup on int0 */ is_power_down = 0; is_power_down_led_int0 = 0; /*open external interrupt 0 power-down wake-up led indicator */ while (power_down_wakeup_pin_int0 == 0) { /* wait higher */ } is_power_down_led_int0 = 1; /* close external interrupt 0 power-down wake-up led indicator */ } 13
else { not_power_down_led_int0 = 0; /* open external interrupt 0 normal work led */ while (power_down_wakeup_pin_int0 ==0) { /* wait higher */ } not_power_down_led_int0 = 1; /* close external interrupt 0 normal work led */ } } void int1_routine (void) interrupt 2 { if (is_power_down) { //is_power_down ==1; /* power-down wakeup on int1 */ is_power_down = 0; is_power_down_led_int1= 0; /*open external interrupt 1 power-down wake-up led indicator */ while (power_down_wakeup_pin_int1 == 0) { /* wait higher */ } is_power_down_led_int1 = 1; /* close external interrupt 1 power-down wake-up led indicator */ } else { not_power_down_led_int1 = 0; /* open external interrupt 1 normal work led */ while (power_down_wakeup_pin_int1 ==0) { /* wait higher */ } not_power_down_led_int1 = 1; /* close external interrupt 1 normal work led */ } } void delay (void) { unsigned int j = 0x00; unsigned int k = 0x00; for (k=0; k<2; ++k) { for (j=0; j<=30000; ++j) { _nop_( ); _nop_( ); _nop_( ); _nop_( ); 14
_nop_( ); _nop_( ); _nop_( ); _nop_( ); } } } void normal_work_flashing (void) { normal_work_flashing_led = 0; delay ( ); normal_work_flashing_led = 1; delay ( ); } the following program also demostrates that power-down mode or idle mode be woken-up by external interrupt, but is written in assembly language rather than c languge. ;************************************************************** ;wake up idle and wake up power down ;************************************************************** org 0000h ajmp main org 0003h int0_interrupt: clr p1.7 ;open p1.7 led indicator acall delay ;delay in order to observe clr ea ;clear global enable bit, stop all interrupts reti org 0013h int1_interrupt: clr p1.6 ;open p1.6 led indicator acall delay ;;delay in order to observe clr ea ;clear global enable bit, stop all interrupts reti org 0100h delay: clr a mov r0, a mov r1, a mov r2, #02 delay_loop: djnz r0, delay_loop djnz r1, delay_loop djnz r2, delay_loop ret 15
main: mov r3, #0 ;p1 led increment mode changed ;start to run program main_loop: mov a, r3 cpl a mov p1, a acall delay inc r3 mov a, r3 subb a, #18h jc main_loop mov p1, #0ffh ;close all led, mcu go into power-down mode clr it0 ;low electrical level trigger external interrupt 0 ; setb it0 ;negative edge trigger external interrupt 0 setb ex0 ;enable external interrupt 0 clr it1 ;low electrical level trigger external interrupt 1 ; setb it1 ;negative edge trigger external interrupt 1 setb ex1 ;enable external interrupt 1 setb ea ;set the global enable ;if don't so, power-down mode cannot be wake up ;mcu will go into idle mode or power-down mode after the following instructions mov pcon, #00000010b ;set pd bit, power-down mode (pd = pcon.1) ; nop ; nop ; nop ; mov pcon, #00000001b ;set idl bit, idle mode (idl = pcon.0) mov p1, #0dfh ;1101, 1111 nop nop nop wait1: sjmp wait1 ;dynamically stop end 2.2 reset control in stc89xx series, there are 5 sources to generate internal reset. they are reset pin, on-chip power-on-reset, watch-dog-timer, software reset, and on-chip max810 por timing delay. 2.2.1 reset pin the rst pin, which is the input to schmitt trigger, is input pin for chip reset. a level change of reset pin have to keep at least 24 cycles plus 10us in order for cpu internal sampling use. when this signal is brought high for at least two machine cycles plus 10 us, the internal registers are loaded with appropriate values for an orderly system start-up. for normal operation, rst is low. 16
2.2.2 power-on reset (por) when vcc drops below the detection threshold of por circuit, all of the logic circuits are reset. when vcc goes back up again, an internal reset is released automatically after a delay of 32768 clocks. the nominal por detection threshold is around 2.0v for 3v device and 3.3v for 5v device. the power-on flag, pof/pcon.4, is set by hardware to denote the vcc power has ever been less than the por voltage. and, it helps users to check if the start of running of the cpu is from power-on or from hardware reset (rst-pin reset), software reset or watchdog timer reset. the pof bit should be cleared by software. pcon register (power control register) lsb bit b7 b6 b5b4b3b2b1b0 name smod smod0 - pof gf1 gf0 pd idl pof : power-on flag. it is set by power-off-on action and can only cleared by software. 2.2.3 watch-dog-timer the watch dog timer in stc89xx series mcu consists of an 8-bit pre-scaler timer and an 15-bit timer. the timer is one-time enabled by setting en_wdt(wdt_contr.5). clearing en_wdt can stop wdt counting. when the wdt is enabled, software should always reset the timer by writing 1 to clr_wdt bit before the wdt overflows. if stc89xx series mcu is out of control by any disturbance, that means the cpu can not run the software normally, then wdt may miss the "writting 1 to clr_wdt" and overflow will come. an overflow of watch-dog-timer will generate a internal reset. 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 8-bit prescalar 15-bit timer - - en_wdt clr_wdt idle_wdt ps2 ps1 ps0 sysclk/12 idl/pcon.0 wdt_contr wdt structure wdt_contr: watch-dog-timer control register lsb bit b7b6 b5 b4 b3 b2b1b0 name - - en_wdt clr_wdt idle_wdt ps2 ps1 ps0 17
wdt overflow time is shown as the bellowed table when sysclk=12mhz and mcu in 12t mode: ps2 ps1 ps0 pre-scale wdt overflow time @12mhz and 12t mode 0 0 0 2 65.5 ms 0 0 1 4 131.0 ms 0 1 0 8 262.1 ms 0 1 1 16 524.2 ms 1 0 0 32 1.0485 s 1 0 1 64 2.0971 s 1 1 0 128 4.1943 s 1 1 1 256 8.3886 s wdt overflow time is shown as the bellowed table when sysclk=11.0592mhz and mcu in 12t mode: ps2 ps1 ps0 pre-scale wdt overflow time @11.0592mhz and 12t mode 0 0 0 2 71.1 ms 0 0 1 4 142.2 ms 0 1 0 8 284.4 ms 0 1 1 16 568.8 ms 1 0 0 32 1.1377 s 1 0 1 64 2.2755 s 1 1 0 128 4.5511 s 1 1 1 256 9.1022 s ps2 ps1 ps0 pre-scale wdt overflow time @20mhz and 12t mode 0 0 0 2 39.3 ms 0 0 1 4 78.6 ms 0 1 0 8 157.3 ms 0 1 1 16 314.6 ms 1 0 0 32 629.1 ms 1 0 1 64 1.25 s 1 1 0 128 2.5 s 1 1 1 256 5 s the wdt overflow time is determined by the following equation: wdt overflow time = (n pre-scale 32768) / sysclk when mcu in 12t mode, n=12; when mcu in 6t mode, n=6 the sysclk=20mhz and mcu in 12t mode in the table above. if sysclk=12mhz and mcu in 12t mode, the wdt overflow time is : wdt overflow time = (12 pre-scale 32768) / 12000000 = pre-scale 393216 / 12000000 en_wdt : enable wdt bit. when set, wdt is started. clr_wdt : wdt clear bit. when set, wdt will recount. hardware will automatically clear this bit. idle_wdt : wdt idle mode bit. when set, wdt is enabled in idle mode. when clear, wdt is disabled in idle. ps2, ps1, ps0 : wdt pre-scale value set bit. pre-scale value of watchdog timer is shown as the bellowed table : 18
the following example is a assembly language program that demostrates stc89xx series mcu wdt. ;/*------------------------------------------------------------------*/ ;/* --- stc mcu international limited -------------------------------*/ ;/* --- stc89xx series mcu wdt demo -----------------------*/ ;/* if you want to use the program or the program referenced in the */ ;/* article, please specify in which data and procedures from stc */ ;/*------------------------------------------------------------------*/ ; wdt overflow time = (n pre-scale 32768) / sysclk ;when mcu in 12t mode, n=12. when mcu in 6t mode, n=6 wdt_contr equ 0e1h ;wdt address led equ p1.5 ;wdt overflow time led on p1.5 ;the wdt overflow time may be measured by the led light time pre_scale_word equ 0x35 ;start up wdt, pre-scale value is 64 ;sysclk=18.432, mcu in 12t mode ,wdt overflow time= 12 x 64 x 32768)/18432000 = 1.36 s org 0000h ajmp main org 0100h main: clr led ;turn led indicator on acall delay ;delay about 1s mov wdt_contr, #pre_scale_word ;start up wdt setb led ;turn off led wait: sjmp wait ;wait wdt overflow reset ;led will be turned on again after reset delay: mov r0, #0 mov r1, #0 mov r2, #15 delay_loop: djnz r0, delay_loop djnz r1, delay_loop djnz r2, delay_loop ret end 19
2.2.4 software reset writing an ?1? to swrst bit in isp_contr register will generate a internal reset. isp_contr: isp/iap control register lsb bit b7 b6 b5 b4 b3 b2b1b0 name ispen swbs swrst - - wt2 wt1 wt0 ispen : isp/iap operation enable. 0 : global disable all isp/iap program/erase/read function. 1 : enable isp/iap program/erase/read function. swbs: software boot selection control. 0 : boot from main-memory after reset. 1 : boot from isp memory after reset. swrst: software reset trigger control. 0 : no operation 1 : generate software system reset. it will be cleared by hardware automatically. b4 ~ b3: reserved. wt2~wt0 : isp/iap waiting time selection while flash is busy. 2.2.5 max810 power-on-reset delay there is another on-chip por delay circuit is integrated on stc89xx. this circuit is max810?sepcial reset circuit and is controlled by configuring flash option register. very long por delay time ? around 400ms will be generated by this circuit once it is enabled. 20
chapter 3 memory organization 3.1 program memory the stc89xx series mcu has separate address space for program memory and data memory. program memory is the memory which stores the program codes for the cpu to execute. there is up to 64k-bytes long of flash memory for program and data storage in the stc89xx series mcu. the lower 4k for the stc89c51rc(8k for the stc89c52rc,16k for stc89c54rc, etc.) may reside on chip. the design allows users to configure it as like there are three individual partition banks inside. they are called ap(application program) region, iap(in- application-program) region and isp(in-system-program) boot region. ap region is the space that user program is resided. iap(in-application-program) region is the nonvolatile data storage space that may be used to save important parameters by ap program. in other words, the iap capability of stc89xx series provide the user to read/write the user-defined on-chip data flash region to save the needing in use of external eeprom device. isp boot region is the space that allows a specific program we calls ?isp program? is resided. inside the isp region, the user can also enable read/write access to a small memory space to store parameters for specific purposes. generally, the purpose of isp program is to fulfill ap program upgrade without the need to remove the device from system. stc89xx series hardware catches the configuration information since power-up duration and performs out-of-space hardware-protection depending on pre-determined criteria. the criteria is ap region can be accessed by isp program only, iap region can be accessed by isp program and ap program, and isp region is prohibited access from ap program and isp program itself. but if the ?isp data flash is enabled?, isp program can read/write this space. when wrong settings on isp-iap sfrs are done, the ?out-of-space? happens and stc89xx series follow the criteria above, ignore the trigger command. after reset, the cpu begins execution from the location 0000h of program memory, where should be the starting of the user?s application code. to service the interrupts, the interrupt service locations (called interrupt vectors) should be located in the program memory. each interrupt is assigned a fixed location in the program memory. the interrupt causes the cpu to jump to that location, where it commences execution of the service routine. external interrupt 0, for example, is assigned to location 0003h. if external interrupt 0 is going to be used, its service routine must begin at location 0003h. if the interrupt is not going to be used, its service location is available as general purpose program memory. the interrupt service locations are spaced at an interval of 8 bytes: 0003h for external interrupt 0, 000bh for timer 0, 0013h for external interrupt 1, 001bh for timer 1, etc. if an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. ffffh 0000h 64k bytes external stc89c51rc program memory 4k bytes internal 60k bytes external or 0000h 0fffh 1000h ffffh ffffh 0000h 64k bytes external stc89c52rc program memory 8k bytes internal 56k bytes external or 0000h 1fffh 2000h ffffh 21
3.2 data memory 3.2.1 on-chip scratch-pad ram just the same as the conventional 8051 micro-controller, there are 256 bytes of sram data memory including 128 bytes of sfr space available on the stc89xx series. the lower 128 bytes of data memory may be accessed through both direct and indirect addressing. the upper 128 bytes of data memory and the 128 bytes of sfr space share the same address space. the upper 128 bytes of data memory may only be accessed using indirect addressing. the 128 bytes of sfr can only be accessed through direct addressing. the lowest 32 bytes (00h~1fh) of data memory are grouped into 4 banks of 8 registers each. program instructions call out these registers as r0 through r7. the rs0 and rs1 bits in psw register(refer to section 3.2.4) select which register bank is in use. instructions using register addressing will only access the currently specified bank.this allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. the next 16 bytes (20h~2fh) above the register banks form a block of bit-addressable memory space. the 80c51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h through 7fh. all of the bytes in the lower 128 can be accessed by either direct or indirect addressing while the upper 128 can only be accessed by indirect addressing. sfrs include the port latches, timers, peripheral controls, etc. these registers can only be accessed by direct addressing. sixteen addresses in sfr space are both byte- and bit- addressable. the bit-addressable sfrs are those whose address ends in 0h or 8h. 3.2.2 auxiliary ram there are 1024 bytes of additional data ram available on stc89c54rd+ series (while 256 bytes of additional data ram are available on stc89c51rc). they may be accessed by the instructions movx @ri or movx @dptr. a control bit ? extram located in auxr.1 register (refer to section 3.2.4) is to control access of auxiliary ram. when set, disable the access of auxiliary ram. when clear (extram=0), this auxiliary ram is the default target for the address range from 0x0000 to 0x03ff and can be indirectly accessed by move external instruction, ?movx @ri? and ?movx @dptr?. if extram=0 and the target address is over 0x03ff, switches to access external ram automatically. when extram=0, the content in dph is ignored when the instruction movx @ri is executed. for keil-c51 compiler, to assign the variables to be located at auxiliary ram, the ?pdata? or ?xdata? definition should be used. after being compiled, the variables declared by ?pdata? and ?xdata? will become the memories accessed by ?movx @ri? and ?movx @dptr?, respectively. thus the stc89xx series mcu hardware can access them correctly. 3.2.3 external ram there is 64k-byte addressing space available for stc89xx series to access external data ram. just the same as the design in the conventional 8051, the port ? p2, p0, ale, p3.6 and p3.7 have alterative function for external data ram access. to access the external data memory, the extram bit should be set to 1. accesses to external data memory can use either a 16-bit address (using ?movx @dptr?) or an 8-bit address (using ?movx @ri?). 8-bit addresses are often used in conjunction with one or more other i/o lines to page the ram. if an 8-bit address is being used, the contents of the port 2 sfr remain at the port 2 pins throughout the external memory cycle. this will facilitate paging access. 16-bit addresses are often used to access up to 64k bytes of external data memory. 22
3.2.4 special function register for ram some sfrs related to ram are shown as follow. for fast data movement, stc89xx series support two data pointers. they share the same sfr address and are switched by the register bit ? dps/auxr1.0. ff 80 special function registers (sfrs) 7f 00 low 128 bytes internal ram ffff 0000 64k bytes external ram external ram high 128 bytes internal ram on-chip scratch-pad ram 1024 bytes expanded ram 03ff 0000 auxiliary ram bank 0 bank 0 bank 0 bank 0 bit addressable 07h 0fh 17h 1fh 00h 08h 10h 18h 20h 30h 2fh 7fh lower 128 bytes of internal sram psw register bit b7b6b5b4b3b2b1b0 name cy ac f0 rs1 rs0 ov f1 p cy : carry flag. ac : auxilliary carry flag.(for bcd operations) f0 : flag 0.(available to the user for general purposes) rs1: register bank select control bit 1. rs0: register bank select control bit 0. ov : overflow flag. f1 : flag 1. user-defined flag. p : parity flag. 23
auxr register bit b7 b6 b5 b4 b3 b2 b1 b0 name - - - - - - extram aleoff b7 ~ b3 : resevered. extram : internal/external ram access 0 : for rd+ series, on-chip auxiliary ram is enabled and located at the address 0x0000 to 0x03ff. and if address over 0x03ff, off-chip external ram becomes the target automatically. for rc seires, on-chip auxiliary ram is enabled and located at the address 00h to ffh. and if address over ffh, off-chip external ram becomes the target automatically. 1 : on-chip auxiliary ram is always disabled. aleoff : disable/enable ale 0 : ale is emitted at a constant rate of 1/3 the system clock in 6t mode, 1/6 sysclk in 12t mode. 1 : ale is active only during a movx or movc instruction. auxr1 register bit b7 b6 b5 b4 b3 b2 b1 b0 name - - - - gf2 - - dps gf2 : general purpose user-defined flag. it can be used by software. dps : dptr registers select bit. 0 : dptr0 is selected(default). 1 : the secondary dptr(dptr 1) is switched to use. external ram 63kb auxiliary ram 1kb 0x0000 0x03ff 0x0400 0xffff external ram 64kb ffffh extram=0 extram=1 0000h 24
an example program for internal expanded ram demo of stc89c58rd+: ;/*------------------------------------------------------------------*/ ;/* --- stc mcu international limited -------------------------------*/ ;/* --- stc89xx series mcu internal expanded ram demo -----------------------*/ ;/* if you want to use the program or the program referenced in the */ ;/* article, please specify in which data and procedures from stc */ ;/*------------------------------------------------------------------*/ #include #include /* use _nop_( ) function */ sfr auxr = 0x8e; sfr auxr1 = 0xa2; sfr p4 = 0xe8; sfr xicon = 0xc0; sfr iph = 0xb7; sfr wdt_contr = 0xe1; sfr isp_data = 0xe2; sfr isp_addrh = 0xe3; sfr isp_addrl = 0xe4; sfr isp_cmd = 0xe5; sfr isp_trig = 0xe6; sfr isp_contr = 0xe7; sbit errom_led = p1^5; sbit ok_led = p1^7; void main ( ) { unsigned int array_point = 0; /*test-array: test_array_one[512], test_array_two[512] */ unsigned char xdata test_array_one[512] = { 0x00, 0x01 0x02, 0x03, 0x04 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f 25
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb ,0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, 0xff, 0xfe, 0xfd, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8, 0xf7, 0xf6, 0xf5, 0xf4, 0xf3, 0xf2, 0xf1, 0xf0, 0xef, 0xee, 0xed, 0xec, 0xeb, 0xea, 0xe9, 0xe8, 0xe7, 0xe6, 0xe5, 0xe4, 0xe3, 0xe2, 0xe1, 0xe0, 0xdf, 0xde, 0xdd, 0xdc, 0xdb, 0xda, 0xd9, 0xd8, 0xd7, 0xd6, 0xd5, 0xd4, 0xd3, 0xd2, 0xd1, 0xd0, 0xcf, 0xce, 0xcd, 0xcc, 0xcb, 0xca, 0xc9, 0xc8, 0xc7, 0xc6, 0xc5, 0xc4, 0xc3, 0xc2, 0xc1, 0xc0, 0xbf, 0xbe, 0xbd, 0xbc, 0xbb, 0xba, 0xb9, 0xb8, 0xb7, 0xb6, 0xb5, 0xb4, 0xb3, 0xb2, 0xb1, 0xb0, 0xaf, 0xae, 0xad, 0xac, 0xab, 0xaa, 0xa9, 0xa8, 0xa7, 0xa6, 0xa5, 0xa4, 0xa3, 0xa2, 0xa1, 0xa0, 0x9f, 0x9e, 0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x7f, 0x7e, 0x7d, 0x7c, 0x7b, 0x7a, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72, 0x71, 0x70, 0x6f, 0x6e, 0x6d, 0x6c, 0x6b, 0x6a, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 26
0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 }; unsigned char xdata test_array_two[512] = { 0x00, 0x01 0x02, 0x03, 0x04 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb ,0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, 0xff, 0xfe, 0xfd, 0xfc, 0xfb, 0xfa, 0xf9, 0xf8, 0xf7, 0xf6, 0xf5, 0xf4, 0xf3, 0xf2, 0xf1, 0xf0, 0xef, 0xee, 0xed, 0xec, 0xeb, 0xea, 0xe9, 0xe8, 0xe7, 0xe6, 0xe5, 0xe4, 0xe3, 0xe2, 0xe1, 0xe0, 27
0xdf, 0xde, 0xdd, 0xdc, 0xdb, 0xda, 0xd9, 0xd8, 0xd7, 0xd6, 0xd5, 0xd4, 0xd3, 0xd2, 0xd1, 0xd0, 0xcf, 0xce, 0xcd, 0xcc, 0xcb, 0xca, 0xc9, 0xc8, 0xc7, 0xc6, 0xc5, 0xc4, 0xc3, 0xc2, 0xc1, 0xc0, 0xbf, 0xbe, 0xbd, 0xbc, 0xbb, 0xba, 0xb9, 0xb8, 0xb7, 0xb6, 0xb5, 0xb4, 0xb3, 0xb2, 0xb1, 0xb0, 0xaf, 0xae, 0xad, 0xac, 0xab, 0xaa, 0xa9, 0xa8, 0xa7, 0xa6, 0xa5, 0xa4, 0xa3, 0xa2, 0xa1, 0xa0, 0x9f, 0x9e, 0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x7f, 0x7e, 0x7d, 0x7c, 0x7b, 0x7a, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72, 0x71, 0x70, 0x6f, 0x6e, 0x6d, 0x6c, 0x6b, 0x6a, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 }; error_led = 1; ok_led = 1; for (array_point = 0; array_point<512; array_point++) { if (test_array_one[array_point] != test_array_two [array_point]) { error_led = 0; ok_led = 1; break; } else{ ok_led = 0; error_led = 1; } } while (1); } 28
chapter 4 configurable i/o ports configurations the stc89xx series mcu has following i/o ports: p0.0~p0.7, p1.0~p1.7, p2.0~p2.7, p3.0~p3.7, p4.0~p4.3(only be available to lqfp44 and plcc44). all port pins on stc89xx series may be independently configured to one of four modes : quasi-bidirectional (standard 8051 port output), push-pull output, input-only or open-drain output .all port pins default to quasi-bidirectional after reset. each one has a schmitt-triggered input for improved input noise rejection. 4.1 quasi-bidirectional i/o port pins in quasi-bidirectional output mode function similar to the standard 8051 port pins. a quasi-bidirectional port can be used as an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin outputs low, it is driven strongly and able to sink a large current. there are three pull-up transistors in the quasi- bidirectional output that serve different purposes. one of these pull-ups, called the ?very weak? pull-up, is turned on whenever the port register for the pin contains a logic ?1?. this very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the ?weak? pull-up, is turned on when the port register for the pin contains a logic ?1? and the pin itself is also at a logic ?1? level. this pull-up provides the primary source current for a quasi- bidirectional pin that is outputting a 1. if this pin is pulled low by the external device, this weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage. the third pull-up is referred to as the ?strong? pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port register changes from a logic ?0? to a logic ?1?. when this occurs, the strong pull-up turns on for two cpu clocks, quickly pulling the port pin high. vcc 2 clock delay vcc vcc port pin weak very weak strong port latch data input data quasi-bidirectional output 29
4.4 open-drain output the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains a logic ?0?. to use this configuration in application, a port pin must have an external pull-up, typically tied to vcc. the pull-down for this mode is the same as for the quasi-bidirectional mode. t he input path of the port pin in this configuration is the same as quasi- bidirection mode. port pin port latch data input data open-drain output 4.3 input-only mode the input-only configuration is a schmitt-triggered input without any pull-up resistors on the pin. port pin input data input-only mode 4.2 push-pull output the push-pull output configuration has the same pull-down structure as both the open-drain and the quasi- bidirectional output modes, but provides a continuous strong pull-up when the port register conatins a logic ?1?. the push-pull mode may be used when more source current is needed from a port output. in addition, input path of the port pin in this configuration is also the same as quasi-bidirectional mode. vcc port pin port latch data input data push-pull output 30
chapter 5 instruction system 5.1 special function registers 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f 0f8h 0ffh 0f0h b 0f7h 0000,0000 0e8h p4 0efh xxxx, 1111 0e0h acc wdt_conr isp_data isp_addrh isp_addrl isp_cmd isp_trig isp_contr 0e7h 0000,0000 xx00,0000 1111,1111 0000,0000 0000,0000 xxxx,x000 xxxx,xxxx 000x,x000 0d8h 0dfh 0d0h psw 0d7h 0000,0000 0c8h t2con t2mod rcap2l rcap2h tl2 th2 0cfh 0000,0000 xxxx,xx00 0000,0000 0000,0000 0000,0000 0000,0000 0c0h xicon 0c7h 0000,0000 0b8h ip saden 0bfh x0x0,0000 0000,0000 0b0h p3 iph 0b7h 1111,1111 0000,0000 0a8h ie saddr 0afh 0000,0000 0000,0000 0a0h p2 auxr1 don't use 0a7h 1111,1111 xxxx,0xx0 098h scon sbuf 09fh 0000,0000 xxxx,xxxx 090h p1 097h 1111,1111 088h tcon tmod tl0 tl1 th0 th1 auxr 08fh 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 xxxx,xx00 080h p0 sp dpl dph pcon 087h 1111,1111 0000,0111 0000,0000 0000,0000 00x1,0000 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f 31
symbol description address bit address and symbol msb lsb value after power-on or reset p0 port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 1111 1111b sp stack pointer 81h 0000 0111b dptr dpl dph data pointer low 82h 0000 0000b data pointer high 83h 0000 0000b pcon power control 87h smod smod0 - pof gf1 gf0 pd idl 00x1 0000b tcon timer/counter 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0000 0000b tmod timer/counter 0 and 1 modes 89h gate c/t m1 m0 gate c/t m1 m0 0000 0000b tl0 timer/counter 0 low byte 8ah 0000 0000b tl1 timer/counter 1 low byte 8bh 0000 0000b th0 timer/counter 0 high byte 8ch 0000 0000b th1 timer/counter 1 high byte 8dh 0000 0000b auxr auxiliary register 0 8eh - - - - - - extram aleoff xxxx xx00b p1 port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 1111 1111b scon serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 0000 0000b sbuf serial buffer 99h xxxx xxxxb p2 port 2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 1111 1111b auxr1 auxiliary register1 a2h - - - - gf2 - - dps 0xxx 0xx0b ie interrupt enable a8h ea - et2 es et1 ex1 et0 ex0 0000 0000b saddr slave address a9h 0000 0000b p3 port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 1111 1111b iph interrupt priority high b7h px3h px2h pt2h psh pt1h px1h pt0h px0h 0000 0000b ip interrupt priority low b8h -- pt2 ps pt1 px1 pt0 px0 xx00 0000b saden slave address mask b9h 0000 0000b xicon auxiliary interrupt control c0h px3 ex3 ie3 it3 px2 ex2 ie2 it2 0000 0000b t2con timer/counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 0000 0000b t2mod timer/counter 2 mode c9h - - - - - - t2oe dcen xxxx xx00b rcap2l timer/counter 2 reload/capture low byte cah 0000 0000b 32
symbol description address bit address and symbol msb lsb value after power-on or reset rcap2h timer/counter 2 reload/capture high byte cbh 0000 0000b tl2 timer/counter low byte cch 0000 0000b th2 timer/counter high byte cdh 0000 0000b psw program status word d0h cy ac f0 rs1 rs0 ov f1 p 0000 0000b acc accumulator e0h 0000 0000b- wdt_contr watch-dog-timer control register e1h - - en_wdt clr_wdt idle_wdt ps2 ps1 ps0 xx00 0000b isp_data isp/iap flash data register e2h 1111 1111b isp_addrh isp/iap flash address high e3h 0000 0000b isp_addrl isp/iap flash address low e4h 0000 0000b isp_cmd isp/iap flash command register e5h -----ms2ms1ms0 xxxx x000b isp_trig isp/iap flash command trigger e6h xxxx xxxxb isp_contr isp/iap control register e7h ispen swbs swrst - - wt2 wt1 wt0 000x x000b p4 port 4 e8h p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 1111 1111b b b register f0h 0000 0000b accumulator acc is the accumulator register. the mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as a. b-register the b register is used during multiply and divide operations. for other instructions it can be treated as another scratch pad register. stack pointer the stack pointer register is 8 bits wide. it is incrementde before data is stored during push and call executions. while the stack may reside anywhee in on-chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at location 08h. 33
program status word(psw) the program status word(psw) contains several status bits that reflect the current state of the cpu. the psw, shown below, resides in the sfr space. it contains the carry bit, the auxiliary carry(for bcd operation), the two register bank select bits, the overflow flag, a parity bit and two user-definable status flags. the carry bit, other than serving the function of a carry bit in arithmetic operations, also serves as the ?accumulator? for a number of boolean operations. the bits rs0 and rs1 are used to select one of the four register banks shown in the previous page. a number of instructions refer to these ram locations as r0 through r7. the parity bit reflects the number of 1s in the accumulator. p=1 if the accumulator contains an odd number of 1s and otherwise p=0. psw register bit76543210 name cy ac f0 rs1 rs0 ov f1 p cy : carry flag. ac : auxilliary carry flag.(for bcd operations) f0 : flag 0.(available to the user for general purposes) rs1: register bank select control bit 1. rs0: register bank select control bit 0. ov : overflow flag. f1 : flag 1. user-defined flag. p : parity flag. data pointer the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). its intended function is to hold a 16-bit address. it may be manipulated as a 16-bit register or as two independent 8-bit registers. for fast data movement, stc89xx series support two data pointers. they share the same sfr address and are switched by the register bit ? dps/auxr1.0. auxr1 register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name - - - - gf2 - - dps gf2 : general purpose user defined flag. it can be used by software. dps : dptr registers select bit. 0 : dptr0 is selected(default). 1 : the secondary dptr(dptr 1) is switched to use. 34
the following program is an assembly program that demostrates how the dual data pointer be used. auxr1 data 0a2h ;define special function register auxr1 mov auxr1, #0 ;dps=0, select dptr0 mov dptr, #1ffh ;set dptr0 for 1ffh mov a, #55h movx @dptr, a ;load the value 55h in the 1ffh unit mov dptr, #2ffh ;set dptr0 for 2ffh mov a, #0aah movx @dptr, a ;load the value 0aah in the 2ffh unit inc auxr1 ;dps=1, dptr1 is selected mov dptr, #1ffh ;set dptr1 for 1ffh movx a, @dptr ;get the content of 1ffh unit ;which is pointed by dptr1, ;the content of accumulator has changed for 55h inc auxr1 ;dps=0, dptr0 is selected movx a, @dptr ;get the content of 2ffh unit ;which is pointed by dptr0, ;the content of accumulator has changed for 0aah inc auxr1 ;dps=1, dptr1 is selected movx a, @dptr ;get the content of 1ffh unit ;which is pointed by dptr1, ;the content of accumulator has changed for 55h inc auxr1 ;dps=0, dptr0 is selected movx a, @dptr ;get the content of 2ffh unit ;which is pointed by dptr0, ;the content of accumulator has changed for 0aah 35
register-specific instruction some instructions are specific to a certain register. for example, some instructions always operate on the accumulator or data pointer,etc. no address byte is needed for such instructions. the opcode itself does it. immediate constant(imm) the value of a constant can follow the opcode in the program memory. index addressing only program memory can be accessed with indexed addressing and it can only be read. this addressing mode is intended for reading look-up tables in program memory. a 16-bit base register(either dptr or pc) points to the base of the table, and the accumulator is set up with the table entry number. another type of indexed addressing is used in the conditional jump instruction. in conditional jump, the destination address is computed as the sum of the base pointer and the accumulator. 5.2 addressing modes addressing modes are an integral part of each computer's instruction set. they allow specifyng the source or destination of data in different ways, depending on the programming situation. there eight modes available: register direct indirect immediate relative absolute long indexed direct addressing(dir) in direct addressing the operand is specified by an 8-bit address field in the instruction. only internal data ram and sfrs can be direct addressed. indirect addressing(ind) in indirect addressing the instruction specified a register which contains the address of the operand. both internal and external ram can be indirectly addressed. the address register for 8-bit addresses can be r0 or r1 of the selected bank, or the stack pointer. the address register for 16-bit addresses can only be the 16-bit data pointer register ? dptr. register instruction(reg) the register banks, containing registers r0 through r7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. instructions that access the registers this way are code efficient because this mode eliminates the need of an extra address byte. when such instruction is executed, one of the eight registers in the selected bank is accessed. ? ? ? ? ? ? ? ? 36
5.3 instruction set summary mnemonic description byte execution clocks of stc 12t mcu execution clocks of stc 6t mcu arithmetic operations add a, rn add register to accumulator 1 12 6 add a, direct add ditect byte to accumulator 2 12 6 add a, @ri add indirect ram to accumulator 1 12 6 add a, #data add immediate data to accumulator 2 12 6 addc a, rn add register to accumulator with carry 1 12 6 addc a, direct add direct byte to accumulator with carry 2 12 6 addc a, @ri add indirect ram to accumulator with carry 1 12 6 addc a, #data add immediate data to acc with carry 2 12 6 subb a, rn subtract register from acc wih borrow 1 12 6 subb a, direct subtract direct byte from acc with borrow 2 12 6 subb a, @ri subtract indirect ram from acc with borrow 1 12 6 subb a, #data substract immediate data from acc with borrow 2 12 6 inc a increment accumulator 1 12 6 inc rn increment register 1 12 6 inc direct increment direct byte 2 12 6 inc @ri increment direct ram 1 12 6 dec a decrement accumulator 1 12 6 dec rn decrement register 1 12 6 dec direct decrement direct byte 2 12 6 dec @ri decrement indirect ram 1 12 6 inc dptr increment data pointer 1 24 12 mul ab multiply a & b 1 48 24 div ab divde a by b 1 48 24 da a decimal adjust accumulator 1 12 6 the stc mcu instructions are fully compatible with the standard 8051's,which are divided among five functional groups: arithmetic logical data transfer boolean variable program branching the following tables provides a quick reference chart showing all the 8051 instructions. once you are familiar with the instruction set, this chart should prove a handy and quick source of reference. ? ? ? ? ? all arithmetic instructions execute one machine cycle except the inc dptr instruction (two machine cycles) and the mul ab and div ab instructions (four machine cycles). note that a machine cycle contains 12 clocks and takes 1us if mcu is operating in 12t mode and from a 12mhz clock.while mcu is operating in 6t mode, a machine cycle contains 6 clocks. 37
mnemonic description byte execution clocks stc of 12t mcu execution clocks of stc 6t mcu logical operations anl a, rn and register to accumulator 1 12 6 anl a, direct and direct btye to accumulator 2 12 6 anl a, @ri and indirect ram to accumulator 1 12 6 anl a, #data and immediate data to accumulator 2 12 6 anl direct, a and accumulator to direct byte 2 12 6 anl direct,#data and immediate data to direct byte 3 24 12 orl a, rn or register to accumulator 1 12 6 orl a,direct or direct byte to accumulator 2 12 6 orl a,@ri or indirect ram to accumulator 1 12 6 orl a, #data or immediate data to accumulator 2 12 6 orl direct, a or accumulator to direct byte 2 12 6 orl direct,#data or immediate data to direct byte 3 24 12 xrl a, rn exclusive-or register to accumulator 1 12 6 xrl a, direct exclusive-or direct byte to accumulator 2 12 6 xrl a, @ri exclusive-or indirect ram to accumulator 112 6 xrl a, #data exclusive-or immediate data to accumulator 212 6 xrl direct, a exclusive-or accumulator to direct byte 2 12 6 xrl direct,#data exclusive-or immediate data to direct byte 324 12 clr a clear accumulator 1 12 6 cpl a complement accumulator 1 12 6 rl a rotate accumulator left 112 6 rlc a rotate accumulator left through the carry 112 6 rr a rotate accumulator right 1 12 6 rrc a rotate accumulator right through the carry 112 6 swap a swap nibbles within the accumulator 1 12 6 38
mnemonic description byte execution clocks of stc 12t mcu execution clocks of stc 6t mcu data transfer mov a, rn move register to accumulator 1 12 6 mov a, direct move direct byte to accumulator 2 12 6 mov a,@ri move indirect ram to 1 12 6 mov a, #data move immediate data to accumulator 2 12 6 mov rn, a move accumulator to register 1 12 6 mov rn, direct move direct byte to register 2 24 12 mov rn, #data move immediate data to register 2 12 6 mov direct, a move accumulator to direct byte 2 12 6 mov direct, rn move register to direct byte 2 24 12 mov direct,direct move direct byte to direct 3 24 12 mov direct, @ri move indirect ram to direct byte 2 24 12 mov direct,#data move immediate data to direct byte 3 24 12 mov @ri, a move accumulator to indirect ram 1 12 6 mov @ri, direct move direct byte to indirect ram 2 24 12 mov @ri, #data move immediate data to indirect ram 2 12 6 mov dptr,#data16 move immdiate data to indirect ram 2 12 6 movc a,@a+dptr move code byte relative to dptr to acc 1 24 12 movc a, @a+pc move code byte relative to pc to acc 1 24 12 movx a,@ri move external ram(16-bit addr) to acc 1 24 12 movx a,@dptr move external ram(16-bit addr) to acc 1 24 12 movx @ri, a move acc to external ram(8-bit addr) 1 24 12 movx @dptr,a move acc to external ram (16-bit addr) 1 24 12 push direct push direct byte onto stack 2 24 12 pop direct pop direct byte from stack 2 24 12 xch a,rn exchange register with accumulator 1 12 6 xch a, direct exchange direct byte with accumulator 2 12 6 xch a, @ri exchange indirect ram with accumulator 1 12 6 xchd a, @ri exchange low-order digit indirect ram with acc 112 6 39
mnemonic description byte execution clocks of stc 12t mcu execution clocks of stc 6t mcu boolean variable manipulation clr c clear carry 1 12 6 clr bit clear direct bit 2 12 6 setb c set carry 1 12 6 setb bit set direct bit 2 12 6 cpl c complement carry 1 12 6 cpl bit complement direct bit 2 12 6 anl c, bit and direct bit to carry 2 24 12 anl c, /bit and complement of direct bit to carry 2 24 12 orl c, bit or direct bit to carry 2 24 12 orl c, /bit or complement of direct bit to carry 2 24 12 mov c, bit move direct bit to carry 2 12 6 mov bit, c move carry to direct bit 2 24 12 jc rel jump if carry is set 2 24 12 jnc rel jump if carry not set 2 24 12 jb bit, rel jump if direct bit is set 3 24 12 jnb bit,rel jump if direct bit is not set 3 24 12 jbc bit, rel jump if direct bit is set & clear bit 3 24 12 program branching acall addr11 absolute subroutine call 2 24 12 lcall addr16 long subroutine call 3 24 12 ret return from subroutine 1 24 12 reti return from interrupt 1 24 12 ajmp addr11 absolute jump 2 24 12 ljmp addr16 long jump 3 24 12 sjmp rel short jump (relative addr) 2 24 12 jmp @a+dptr jump indirect relative to the dptr 1 24 12 jz rel jump if accumulator is zero 2 24 12 jnz rel jump if accumulator is not zero 2 24 12 cjne a,direct,rel compare direct byte to acc and jump if not equal 324 12 cjne a,#data,rel compare immediate to acc and jump if not equal 324 12 cjne rn,#data,rel compare immediate to register and jump if not equal 324 12 cjne @ri,#data,rel compare immediate to indirect and jump if not equal 324 12 djnz rn, rel decrement register and jump if not zero 2 24 12 djnz direct, rel decr ement direct byte and jump if not zero 324 12 nop no operation 1 12 6 40
5.4 instruction definitions acall addr 11 function: absolute call description: acall unconditionally calls a subroutine located at the indicated address.the instruction increments the pc twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice. the destination address is obtained by suceesively concatenating the five high-order bits of the incremented pc opcode bits 7-5,and the second byte of the instruction. the subroutine called must therefore start within the same 2k block of the program memory as the first byte of the instruction following acall. no flags are affected. example: initially sp equals 07h. the label ?subrtn? is at program memory location 0345h. after executingthe instruction, acall subrtn at location 0123h, sp will contain 09h, internal ram locations 08h and 09h will contain 25h and 01h, respectively, and the pc will contain 0345h. bytes: 2 cycles: 2 encoding: a10 a9 a8 1 0 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 operation: acall (pc) (pc)+ 2 (pc)+ 2 (pc)+ 2 (sp) (sp) + 1 (sp)+1 (sp) + 1 ((sp)) (pc (pc (pc 7-0 ) (sp) (sp) + 1 (sp)+1 (sp) + 1 ((sp)) (pc (pc (pc 15-8 ) (pc 10-0 ) page address page address page address add a, function: add description: add adds the byte variable indicated to the accumulator, leaving the result in the accumulator. the carry and auxiliary-carry flags are set, respectively, if there is a carry- out from bit 7 or bit 3, and cleared otherwise. when adding unsigned integers, the carry flag indicates an overflow occured. ov is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise ov is cleared. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. four source operand addressing modes are allowed: register,direct register-indirect, or immediate. example: the accumulator holds 0c3h(11000011b) and register 0 holds 0aah (10101010b). the instruction, add a,r0 will leave 6dh (01101101b) in the accumulator with the ac flag cleared and both the carry flag and ov set to 1. 41
add a,rn bytes: 1 cycles: 1 encoding: 0 0 1 0 1 r r r operation: add (a) (a) + (rn) (a) + (rn) (a) + (rn) add a,direct bytes: 2 cycles: 1 encoding: 0 0 1 0 0 1 0 1 direct address operation: add (a) (a) + (direct) (a) + (direct) (a) + (direct) add a,@ri bytes: 1 cycles: 1 encoding: 0 0 1 0 0 1 1 i operation: add (a) (a) + ((ri)) (a) + ((ri)) (a) + ((ri)) add a,#data bytes: 2 cycles: 1 encoding: 0 0 1 0 0 1 0 0 immediate data operation: add (a) (a) + #data (a) + #data (a) + #data addc a, function: add with carry description: addc simultaneously adds the byte variable indicated, the carry flag and the accumulator, leaving the result in the accumulator. the carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. when adding unsigned integers, the carry flag indicates an overflow occured. ov is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise ov is cleared. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. 42
addc a,rn bytes: 1 cycles: 1 encoding: 0 0 1 1 1 r r r operation: addc (a) (a) + (c) + (rn) (a) + (c) + (rn) (a) + (c) + (rn) addc a,direct bytes: 2 cycles: 1 encoding: 0 0 1 1 0 1 0 1 direct address operation: addc (a) (a) + (c) + (direct) (a) + (c) + (direct) (a) + (c) + (direct) addc a,@ri bytes: 1 cycles: 1 encoding: 0 0 1 1 0 1 1 i operation: addc (a) (a) + (c) + ((ri)) (a) + (c) + ((ri)) (a) + (c) + ((ri)) addc a,#data bytes: 2 cycles: 1 encoding: 0 0 1 1 0 1 0 0 immediate data operation: addc (a) (a) + (c) + #data (a) + (c) + #data (a) + (c) + #data ajmp addr 11 function: absolute jump description: ajmp transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the pc (after incrementing the pc twice), opcode bits 7-5, and the second byte of the instruction. the destination must therefore be within the same 2k block of program memory as the first byte of the instruction following ajmp. example: the label ?jmpadr? is at program memory location 0123h. the instruction, ajmp jmpadr is at location 0345h and will load the pc with 0123h. bytes: 2 cycles: 2 encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 operation: ajmp (pc) (pc)+ 2 (pc)+ 2 (pc)+ 2 (pc 10-0 ) page address page address page address 43
anl , function: logical-and for byte variables description: anl performs the bitwise logical-and operation between the variables indicated and stores the results in the destination variable. no flags are affected. the two operands allow six addressing mode combinations. when the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch not the input pins. example: if the accumulator holds 0c3h(11000011b) and register 0 holds 55h (01010101b) then the instruction, anl a,r0 will leave 41h (01000001b) in the accumulator. when the destination is a directly addressed byte, this instruction will clear combinations of bits in any ram location or hardware register. the mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the accumulator at run-time. the instruction, anl pl, #01110011b will clear bits 7, 3, and 2 of output port 1. anl a,rn bytes: 1 cycles: 1 encoding: 0 1 0 1 1 r r r operation: anl (a) (a) (a) (a) ! (rn) anl a,direct bytes: 2 cycles: 1 encoding: 0 1 0 1 0 1 0 1 direct address operation: anl (a) (a) (a) (a) ! (direct) anl a,@ri bytes: 1 cycles: 1 encoding: 0 1 0 1 0 1 1 i operation: anl (a) (a) (a) (a) ! ((ri)) 44
anl a,#data bytes: 2 cycles: 1 encoding: 0 1 0 1 0 1 0 0 immediate data operation: anl (a) (a) (a) (a) ! #data anl direct,a bytes: 2 cycles: 1 encoding: 0 1 0 1 0 0 1 0 direct address operation: anl (direct) (direct) (direct) (direct) ! (a) anl direct,#data bytes: 3 cycles: 2 encoding: 0 1 0 1 0 0 1 1 direct address immediate data operation: anl (direct) (direct) (direct) (direct) ! #data anl c , function: logical-and for bit variables description: if the boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the carry flag in its current state. a slash (? / ?) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affceted. no other flsgs are affected. only direct addressing is allowed for the source operand. example: set the carry flag if, and only if, p1.0 = 1, acc. 7 = 1, and ov = 0: mov c, p1.0 ;load carry with input pin state anl c, acc.7 ;and carry with accum. bit.7 anl c, /ov ;and with inverse of overflow flag anl c,bit bytes: 2 cycles: 2 encoding: 1 0 0 0 0 0 1 0 bit address operation: anl (c) (c) (c) (c) ! (bit) 45
anl c, /bit bytes: 2 cycles: 2 encoding: 1 0 1 1 0 0 0 0 bit address operation: add (c) (c) (c) (c) ! (bit) cjne , , rel function: compare and jump if not equal description: cjne compares the magnitudes of the first two operands, and branches if their values are not equal. the branch destination is computed by adding the signed relative-displacement in the last instruction byte to the pc, after incrementing the pc to the start of the next instruction. the carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. neither operand is affected. the first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data, and any indirect ram location or working register can be compared with an immediate constant. example: the accumulator contains 34h. register 7 contains 56h. the first instruction in the sequence cjne r7,#60h, not-eq ; . . . . . . . . . ; r7 = 60h. not_eq: jc req_low ; if r7 < 60h. ; . . . . . . . . ; r7 > 60h. sets the carry flag and branches to the instruction at label not-eq. by testing the carry flag, this instruction determines whether r7 is greater or less than 60h. if the data being presented to port 1 is also 34h, then the instruction, wait: cjne a,p1,wait clears the carry flag and continues with the next instruction in sequence, since the accumulator does equal the data read from p1. (if some other value was being input on pl, the program will loop at this point until the p1 data changes to 34h.) cjne a,direct,rel bytes: 3 cycles: 2 encoding: 1 0 1 1 0 1 0 1 direct address rel. address operation: (pc) (pc) + 3 (pc) + 3 (pc) + 3 if (a) < > (direct) then (pc) (pc) + (pc) + (pc) + relative offset if (a) < (direct) then (c) 1 1 1 else (c) 0 0 0 46
cjne a,#data,rel bytes: 3 cycles: 2 encoding: 1 0 1 1 0 1 0 1 immediata data rel. address operation: (pc) (pc) + 3 (pc) + 3 (pc) + 3 if (a) < > (data) then (pc) (pc) + (pc) + (pc) + relative offset if (a) < (data) then (c) 1 1 1 else (c) 0 0 0 cjne rn,#data,rel bytes: 3 cycles: 2 encoding: 1 0 1 1 1 r r r immediata data rel. address operation: (pc) (pc) + 3 (pc) + 3 (pc) + 3 if (rn) < > (data) then (pc) (pc) + (pc) + (pc) + relative offset if (rn) < (data) then (c) 1 1 1 else (c) 0 0 0 cjne @ri,#data,rel bytes: 3 cycles: 2 encoding: 1 0 1 1 0 1 1 i immediate data rel. address operation: (pc) (pc) + 3 (pc) + 3 (pc) + 3 if ((ri)) < > (data) then (pc) (pc) + (pc) + (pc) + relative offset if ((ri)) < (data) then (c) 1 1 1 else (c) 0 0 0 47
clr a function: clear accumulator description: the aecunmlator is cleared (all bits set on zero). no flags are affected. example: the accumulator contains 5ch (01011100b). the instruction, clr a will leave the accumulator set to 00h (00000000b). bytes: 1 cycles: 1 encoding: 1 1 1 0 0 1 0 0 operation: clr (a) 0 0 0 clr bit function: clear bit description: the indicated bit is cleared (reset to zero). no other flags are affected. clr can operate on the carry flag or any directly addressable bit. example: port 1 has previously been written with 5dh (01011101b). the instruction, clr p1.2 will leave the port set to 59h (01011001b). clr c bytes: 1 cycles: 1 encoding: 1 1 0 0 0 0 1 1 operation: clr (c) 0 0 0 clr bit bytes: 2 cycles: 1 encoding: 1 1 0 0 0 0 1 0 bit address operation: clr (bit) 0 0 0 48
cpl a function: complement accumulator description: each bit of the accumulator is logically complemented (one?s complement). bits which previously contained a one are changed to a zero and vice-versa. no flags are affected. example: the accumulator contains 5ch(01011100b). the instruction, cpl a will leave the accumulator set to 0a3h (101000011b). bytes: 1 cycles: 1 encoding: 1 1 1 1 0 1 0 0 operation: cpl (a) (a) cpl bit function: complement bit description: the bit variable specified is complemented. a bit which had been a one is changed to zero and vice-versa. no other flags are affected. clr can operate on the carry or any directly addressable bit. note:when this instruction is used to modify an output pin, the value used as the original data will be read from the output data latch, not the input pin. example: port 1 has previously been written with 5dh (01011101b). the instruction, clr p1.1 clr p1.2 will leave the port set to 59h (01011001b). cpl c bytes: 1 cycles: 1 encoding: 1 0 1 1 0 0 1 1 operation: cpl (c) (c) cpl bit bytes: 2 cycles: 1 encoding: 1 0 1 1 0 0 1 0 bit address operation: cpl (bit) (bit) 49
da a function: decimal-adjust accumulator for addition description: da a adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed-bcd format), producing two four-bit digits.any add or addc instruction may have been used to perform the addition. if accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the ac flag is one, six is added to the accumulator producing the proper bcd digit in the low-order nibble. this internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise. if the carry flag is now set or if the four high-order bits now exceed nine(1010xxxx- 111xxxx), these high-order bits are incremented by six, producing the proper bcd digit in the high-order nibble. again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn?t clear the carry. the carry flag thus indicates if the sum of the original two bcd variables is greater than 100, allowing multiple precision decimal addition. ov is not affected. all of this occurs during the one instruction cycle. essentially, this instruction performs the decimal conversion by adding 00h, 06h, 60h, or 66h to the accumulator, depending on initial accumulator and psw conditions. note: da a cannot simply convert a hexadecimal number in the accumulator to bcd notation, nor does da a apply to decimal subtraction. example: the accumulator holds the value 56h(01010110b) representing the packed bcd digits of the decimal number 56. register 3 contains the value 67h (01100111b) representing the packed bcd digits of the decimal number 67.the carry flag is set. the instruction sequence. addc a,r3 da a will first perform a standard twos-complement binary addition, resulting in the value 0beh (101111 10) in the accumulator. the carry and auxiliary carry flags will be cleared. the decimal adjust instruction will then alter the accumulator to the value 24h (00100100b), indicating the packed bcd digits of the decimal number 24, the low-order two digits of the decimal sum of 56,67, and the carry-in. the carry flag will be set by the decimal adjust instruction, indicating that a decimal overflow occurred. the true sum 56, 67, and 1 is 124. bcd variables can be incremented or decremented by adding 01h or 99h. if the accumula- tor initially holds 30h (representing the digits of 30 decimal), then the instruction sequence, add a,#99h da a will leave the carry set and 29h in the accumulator, since 30+99=129. the low-order byte of the sum can be interpreted to mean 30 ? 1 = 29. 50
bytes: 1 cycles: 1 encoding: 1 1 0 1 0 1 0 0 operation: da -contents of accumulator are bcd if [[(a 3-0 ) > 9] v [(ac) = 1]] then(a 3-0 ) (a (a (a 3-0 ) + 6 and if [[(a 7-4 ) > 9] v [(c) = 1]] then (a 7-4 ) (a (a (a 7-4 ) + 6 dec byte function: decrement description: the variable indicated is decremented by 1. an original value of 00h will underflow to 0ffh. no flags are affected. four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: register 0 contains 7fh (01 11111 1b). internal ram locations 7eh and 7fh contain 00h and 40h, respectively. the instruction sequence, dec @r0 dec r0 dec @r0 will leave register 0 set to 7eh and internal ram locations 7eh and 7fh set to 0ffh and 3fh. dec a bytes: 1 cycles: 1 encoding: 0 0 0 1 0 1 0 0 operation: dec (a) (a) (a) (a) dec rn bytes: 1 cycles: 1 encoding: 0 0 0 1 1 r r r operation: dec (rn) (rn) - 1 (rn) - 1 (rn) - 1 51
dec direct bytes: 2 cycles: 1 encoding: 0 0 0 1 0 1 0 1 direct address operation: dec (direct) (direct) (direct) (direct) dec @ri bytes: 1 cycles: 1 encoding: 0 0 0 1 0 1 1 i operation: dec ((ri)) ((ri)) - 1 ((ri)) - 1 ((ri)) - 1 div ab function: divide description: div ab divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register b. the accumulator receives the integer part of the quotient; register b receives the integer remainder. the carry and ov flags will be cleared. exception: if b had originally contained 00h, the values returned in the accumulator and b-register will be undefined and the overflow flag will be set. the carry flag is cleared in any case. example: the accumulator contains 251(ofbh or 1111101 1b) and b contains 18(12h or 00010010b). the instruction, div ab will leave 13 in the accumulator (0dh or 00001101b) and the value 17 (11h or 00010010b) in b, since 251 = (1318) + 17. carry and ov will both be cleared. bytes: 1 cycles: 4 encoding: 1 0 0 0 0 1 0 0 operation: div (a) 15-8 (b) 7-0 (a)/(b) (a)/(b) 52
djnz , function: decrement and jump if not zero description: djnz decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. an original value of 00h will underflow to 0ffh. no flags are afected. the branch destination would be computed by adding the signed relative-displacement value in the last instruction byte to the pc, after incrementing the pc to the first byte of the following instruction. the location decremented may be a register or directly addressed byte. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: internal ram locations 40h, 50h, and 60h contain the values 01h, 70h, and 15h, respectively. the instruction sequence, djnz 40h, label_1 djnz 50h, label_2 djnz 60h, label_3 will cause a jump to the instruction at label label_2 with the values 00h, 6fh, and 15h in the three ram locations. the first jump was not taken because the result was zero. this instruction provides a simple way of executing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction the instruction sequence, mov r2,#8 tooole: cpl p1.7 djnz r2, toogle will toggle p1.7 eight times, causing four output pulses to appear at bit 7 of output port 1. each pulse will last three machine cycles; two for djnz and one to alter the pin. djnz rn,rel bytes: 2 cycles: 2 encoding: 1 1 0 1 1 r r r rel. address operation: djnz (pc) (pc) + 2 (pc) + 2 (pc) + 2 (rn) (rn) ? 1 (rn) ? 1 (rn) ? 1 if (rn) > 0 or (rn) < 0 then (pc) (pc)+ rel (pc)+ rel (pc)+ rel djnz direct, rel bytes: 3 cycles: 2 encoding: 1 1 0 1 0 1 0 1 direct address rel. address 53
operation: djnz (pc) (pc) + 2 (pc) + 2 (pc) + 2 (direct) (direct) ? 1 (direct) ? 1 (direct) ? 1 if (direct) > 0 or (direct) < 0 then (pc) (pc) + rel (pc) + rel (pc) + rel inc function: increment description: inc increments the indicated variable by 1. an original value of 0ffh will overflow to 00h.no flags are affected. three addressing modes are allowed: register, direct, or register- indirect. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: register 0 contains 7eh (01 11111 10b). internal ram locations 7eh and 7fh contain 0ffh and 40h, respectively. the instruction sequence, inc @r0 inc r0 inc @r0 will leave register 0 set to 7fh and internal ram locations 7eh and 7fh holding (respectively) 00h and 41h. inc a bytes: 1 cycles: 1 encoding: 0 0 0 0 0 1 0 0 operation: inc (a) (a)+1 (a)+1 inc rn bytes: 1 cycles: 1 encoding: 0 0 0 0 1 r r r operation: inc (rn) (rn)+1 (rn)+1 inc direct bytes: 2 cycles: 1 encoding: 0 0 0 0 0 1 0 1 direct address operation: inc (direct) (direct) (direct) (direct) 54
inc @ri bytes: 1 cycles: 1 encoding: 0 0 0 0 0 1 1 i operation: inc ((ri)) ((ri)) + 1 ((ri)) + 1 ((ri)) + 1 inc dptr function: increment data pointer description: increment the 16-bit data pointer by 1. a 16-bit increment (modulo 2 16 ) is performed; an overflow of the low-order byte of the data pointer (dpl) from 0ffh to 00h will increment the high-order-byte (dph). no flags are affected. this is the only 16-bit register which can be incremented. example: register dph and dpl contains 12h and 0feh,respectively. the instruction sequence, inc dptr inc dptr inc dptr will change dph and dpl to 13h and 01h. bytes: 1 cycles: 2 encoding: 1 0 1 0 0 0 1 1 operation: inc (dptr) (dptr)+1 (dptr)+1 jb bit, rel function: jump if bit set description: if the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative-displacement in the third instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. example: the data present at input port 1 is 11001010b. the accumulator holds 56 (01010110b). the instruction sequence, jb p1.2, label1 jb acc.2, label2 will cause program execution to branch to the instruction at label label2. bytes: 3 cycles: 2 encoding: 0 0 1 0 0 0 0 0 bit address rel. address operation: jb (pc) (pc)+ 3 (pc)+ 3 (pc)+ 3 if (bit) = 1 then (pc) (pc) + rel (pc) + rel (pc) + rel 55
jbc bit, rel function: jump if bit is set and clear bit description: if the indicated bit is one,branch to the address indicated;otherwise proceed with the next instruction. the bit wili not be cleared if it is already a zero. the branch destination is computed by adding the signed relative-displacement in the third instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. no flags are affected. note: when this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. example: the accumulator holds 56h (01010110b). the instruction sequence, jbc acc.3, label1 jbc acc.2, label2 will cause program execution to continue at the instruction identified by the label label2, with the accumulator modified to 52h (01010010b). bytes: 3 cycles: 2 encoding: 0 0 0 1 0 0 0 0 bit address rel. address operation: jbc (pc) (pc)+ 3 (pc)+ 3 (pc)+ 3 if (bit) = 1 then (bit) 0 0 (pc) (pc) + rel (pc) + rel (pc) + rel jc rel function: jump if carry is set description: if the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative-displacement in the second instruction byte to the pc, after incrementing the pc twice.no flags are affected. example: the carry flag is cleared. the instruction sequence, jc label1 cpl c jc label2s will set the carry and cause program execution to continue at the instruction identified by the label label2. bytes: 2 cycles: 2 encoding: 0 1 0 0 0 0 0 0 rel. address operation: jc (pc) (pc)+ 2 (pc)+ 2 (pc)+ 2 if (c) = 1 then (pc) (pc) + rel (pc) + rel (pc) + rel 56
jmp @a+dptr function: jump indirect description: add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. this will be the address for subsequent instruction fetches. sixteen-bit addition is performed (modulo 2 16 ): a carry-out from the low- order eight bits propagates through the higher-order bits. neither the accumulator nor the data pointer is altered. no flags are affected. example: an even number from 0 to 6 is in the accumulator. the following sequence of instructions will branch to one of four ajmp instructions in a jump table starting at jmp_tbl: mov dptr, #jmp_tbl jmp @a+dptr jmp-tbl: ajmp label0 ajmp label1 ajmp label2 ajmp label3 if the accumulator equals 04h when starting this sequence, execution will jump to label label2. remember that ajmp is a two-byte instruction, so the jump instructions start at every other address. bytes: 1 cycles: 2 encoding: 0 1 1 1 0 0 1 1 operation: jmp (pc) (a) + (dptr) (a) + (dptr) (a) + (dptr) jnb bit, rel function: jump if bit is not set description: if the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative-displacement in the third instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. example: the data present at input port 1 is 11001010b. the accumulator holds 56h (01010110b). the instruction sequence, jnb p1.3, label1 jnb acc.3, label2 will cause program execution to continue at the instruction at label label2 bytes: 3 cycles: 2 encoding: 0 0 1 1 0 0 0 0 bit address rel. address operation: jnb (pc) (pc)+ 3 (pc)+ 3 (pc)+ 3 if (bit) = 0 then (pc) (pc) + rel (pc) + rel (pc) + rel 57
jnc rel function: jump if carry not set description: if the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative-displacement in the second instruction byte to the pc, after incrementing the pc twice to point to the next instruction. the carry flag is not modified example: the carry flag is set. the instruction sequence, jnc label1 cpl c jnc label2 will clear the carry and cause program execution to continue at the instruction identified by the label label2. bytes: 2 cycles: 2 encoding: 0 1 0 1 0 0 0 0 rel. address operation: jnc (pc) (pc)+ 2 (pc)+ 2 (pc)+ 2 if (c) = 0 then (pc) (pc) + rel (pc) + rel (pc) + rel jnz rel function: jump if accumulator not zero description: if any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative- displacement in the second instruction byte to the pc, after incrementing the pc twice. the accumulator is not modified. no flags are affected. example: the accumulator originally holds 00h. the instruction sequence, jnz label1 inc a jnz laeel2 will set the accumulator to 01h and continue at label label2. bytes: 2 cycles: 2 encoding: 0 1 1 1 0 0 0 0 rel. address operation: jnz (pc) (pc)+ 2 (pc)+ 2 (pc)+ 2 if (a) 0 then (pc) (pc) + rel (pc) + rel (pc) + rel 58
jz rel function: jump if accumulator zero description: if all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative- displacement in the second instruction byte to the pc, after incrementing the pc twice. the accumulator is not modified. no flags are affected. example: the accumulator originally contains 01h. the instruction sequence, jz label1 dec a jz laeel2 will change the accumulator to 00h and cause program execution to continue at the instruction identified by the label label2. bytes: 2 cycles: 2 encoding: 0 1 1 0 0 0 0 0 rel. address operation: jz (pc) (pc)+ 2 (pc)+ 2 (pc)+ 2 if (a) = 0 then (pc) (pc) + rel (pc) + rel (pc) + rel lcall addr16 function: long call description: lcall calls a subroutine loated at the indicated address. the instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two. the high-order and low-order bytes of the pc are then loaded, respectively, with the second and third bytes of the lcall instruction. program execution continues with the instruction at this address. the subroutine may therefore begin anywhere in the full 64k-byte program memory address space. no flags are affected. example: initially the stack pointer equals 07h. the label ?subrtn? is assigned to program memory location 1234h. after executing the instruction, lcall subrtn at location 0123h, the stack pointer will contain 09h, internal ram locations 08h and 09h will contain 26h and 01h, and the pc will contain 1234h. bytes: 3 cycles: 2 encoding: 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0 operation: lcall (pc) (pc) + 3 (pc) + 3 (pc) + 3 (sp) (sp)+1 (sp)+1 (sp) + 1 ((sp)) (pc (pc (pc 7-0 ) (sp) (sp)+1 (sp)+1 (sp) + 1 ((sp)) (pc (pc (pc 15-8 ) (pc) addr addr addr 15-0 59
ljmp addr16 function: long jump description: ljmp causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the pc (respectively) with the second and third instruction bytes. the destination may therefore be anywhere in the full 64k program memory address space. no flags are affected. example: the label ?jmpadr? is assigned to the instruction at program memory location 1234h. the instruction, ljmp jmpadr at location 0123h will load the program counter with 1234h. bytes: 3 cycles: 2 encoding: 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0 operation: ljmp (pc) addr addr addr 15-0 mov , function: move byte variable description: the byte variable indicated by the second operand is copied into the location specified by the first operand. the source byte is not affected. no other register or flag is affected. this is by far the most flexible operation. fifteen combinations of source and destination addressing modes are allowed. example: internal ram location 30h holds 40h. the value of ram location 40h is 10h. the data present at input port 1 is 11001010b (0cah). mov r0, #30h ;r0< = 30h mov a, @r0 ;a < = 40h mov r1, a ;r1 < = 40h mov b, @rl ;b < = 10h mov @rl, pl ;ram (40h) < = 0cah mov p2, p1 ;p2 #0cah leaves the value 30h in register 0,40h in both the accumulator and register 1,10h in register b, and 0cah(11001010b) both in ram location 40h and output on port 2. mov a,rn bytes: 1 cycles: 1 encoding: 1 1 1 0 1 r r r operation: mov (a) (rn) (rn) (rn) 60
*mov a,direct bytes: 2 cycles: 1 encoding: 1 1 1 0 0 1 0 1 direct address operation: mov (a) (direct) (direct) (direct) *mov a, acc is not a valid instruction mov a,@ri bytes: 1 cycles: 1 encoding: 1 1 1 0 0 1 1 i operation: mov (a) ((ri)) ((ri)) ((ri)) mov a,#data bytes: 2 cycles: 1 encoding: 0 1 1 1 0 1 0 0 immediate data operation: mov (a) #data #data #data mov rn, a bytes: 1 cycles: 1 encoding: 1 1 1 1 1 r r r operation: mov (rn) (a) (a) (a) mov rn,direct bytes: 2 cycles: 2 encoding: 1 0 1 0 1 r r r direct addr. operation: mov (rn) (direct) (direct) (direct) mov rn,#data bytes: 2 cycles: 1 encoding: 0 1 1 1 1 r r r immediate data operation: mov (rn) #data #data #data 61
mov direct, a bytes: 2 cycles: 1 encoding: 1 1 1 1 0 1 0 1 direct address operation: mov (direct) (a) (a) (a) mov direct, rn bytes: 2 cycles: 2 encoding: 1 0 0 0 1 r r r direct address operation: mov (direct) (rn) (rn) (rn) mov direct, direct bytes: 3 cycles: 2 encoding: 1 0 0 0 0 1 0 1 dir.addr. (src) operation: mov (direct) (direct) (direct) (direct) mov direct, @ri bytes: 2 cycles: 2 encoding: 1 0 0 0 0 1 1 i direct addr. operation: mov (direct) ((ri)) ((ri)) ((ri)) mov direct,#data bytes: 3 cycles: 2 encoding: 0 1 1 1 0 1 0 1 direct address operation: mov (direct) #data #data #data mov @ri, a bytes: 1 cycles: 1 encoding: 1 1 1 1 0 1 1 i operation: mov ((ri)) (a) (a) (a) 62
mov @ri, direct bytes: 2 cycles: 2 encoding: 1 0 1 0 0 1 1 i direct addr. operation: mov ((ri)) (direct) (direct) (direct) mov @ri, #data bytes: 2 cycles: 1 encoding: 0 1 1 1 0 1 1 i immediate data operation: mov ((ri)) #data #data #data mov , function: move bit data description: the boolean variable indicated by the second operand is copied into the location specified by the first operand. one of the operands must be the carry flag; the other may be any directly addressable bit. no other register or flag is affected. example: the carry flag is originally set. the data present at input port 3 is 11000101b. the data previously written to output port 1 is 35h (00110101b). mov p1.3, c mov c, p3.3 mov p1.2, c will leave the carry cleared and change port 1 to 39h (00111001b). mov c,bit bytes: 2 cycles: 1 encoding: 1 0 1 0 0 0 1 1 bit address operation: mov (c) (bit) (bit) (bit) mov bit,c bytes: 2 cycles: 2 encoding: 1 0 0 1 0 0 1 0 bit address operation: mov (bit) (c) (c) (c) 63
mov dptr , #data 16 function: load data pointer with a 16-bit constant description: the data pointer is loaded with the 16-bit constant indicated.the 16-bit constant is loaded into the second and third bytes of the instruction. the second byte (dph) is the high-order byte, while the third byte (dpl) holds the low-order byte. no flags are affected. this is the only instruction which moves 16 bits of data at once. example: the instruction, mov dptr, #1234h will load the value 1234h into the data pointer: dph will hold 12h and dpl will hold 34h. bytes: 3 cycles: 2 encoding: 1 0 0 1 0 0 0 0 immediate data 15-8 operation: mov (dptr) #data #data #data 15-0 dph dpl #data #data 15-8 #data 7-0 movc a , @a+ function: move code byte description: the movc instructions load the accumulator with a code byte, or constant from program memory. the address of the byte fetched is the sum of the original unsigned eight-bit. accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the pc. in the latter case, the pc is incremented to the address of the following instruction before being added with the accumulator; otherwise the base register is not altered. sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. no flags are affected. example: a value between 0 and 3 is in the accumulator. the following instructions will translate the value in the accumulator to one of four values defimed by the db (define byte) directive. rel-pc: inc a movc a, @a+pc ret db 66h db 77h db 88h db 99h if the subroutine is called with the accumulator equal to 01h, it will return with 77h in the accumulator. the inc a before the movc instruction is needed to ?get around? the ret instruction above the table. if several bytes of code separated the movc from the table, the corresponding number would be added to the accumulator instead. movc a,@a+dptr bytes: 1 cycles: 2 encoding: 1 0 0 1 0 0 1 1 operation: movc (a) ((a)+(dptr)) ((a)+(dptr)) ((a)+(dptr)) 64
movc a,@a+pc bytes: 1 cycles: 2 encoding: 1 0 0 0 0 0 1 1 operation: movc (pc) (pc)+1 (pc)+1 (a) ((a)+(pc)) ((a)+(pc)) ((a)+(pc)) movx , function: move external description: the movx instructions transfer data between the accumulator and a byte of external data memory, hence the ?x? appended to mov. there are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data ram. in the first type, the contents of r0 or r1 in the current register bank provide an eight-bit address multiplexed with data on p0. eight bits are sufficient for external i/o expansion decoding or for a relatively small ram array. for somewhat larger arrays, any output port pins can be used to output higher-order address bits. these pins would be controlled by an output instruction preceding the movx. in the second type of movx instruction, the data pointer generates a sixteen-bit address. p2 outputs the high-order eight address bits (the contents of dph) while p0 multiplexes the low-order eight bits (dpl) with data. the p2 special function register retains its previous contents while the p2 output buffers are emitting the contents of dph. this form is faster and more efficient when accessing very large data arrays (up to 64k bytes), since no additional instructions are needed to set up the output ports. it is possible in some situations to mix the two movx types. a large ram array with its high-order address lines driven by p2 can be addressed via the data pointer, or with code to output high-order address bits to p2 followed by a movx instruction using r0 or r1. example: an external 256 byte ram using multiplexed address/data lines (e.g., an intel 8155 ram/ i/o/timer) is connected to the 8051 port 0. port 3 provides control lines for the external ram. ports 1 and 2 are used for normal i/o. registers 0 and 1 contain 12h and 34h. location 34h of the external ram holds the value 56h. the instruction sequence, movx a, @r1 movx @r0, a copies the value 56h into both the accumulator and external ram location 12h. movx a,@ri bytes: 1 cycles: 2 encoding: 1 1 1 0 0 0 1 i operation: movx (a) ((ri)) ((ri)) ((ri)) 65
movx a,@dptr bytes: 1 cycles: 2 encoding: 1 1 1 0 0 0 0 0 operation: movx (a) ((dptr)) ((dptr)) ((dptr)) movx @ri, a bytes: 1 cycles: 2 encoding: 1 1 1 1 0 0 1 i operation: movx ((ri)) (a) (a) (a) movx @dptr, a bytes: 1 cycles: 2 encoding: 1 1 1 1 0 0 0 0 operation: movx (dptr) (a) (a) (a) mul ab function: multiply description: mul ab multiplies the unsigned eight-bit integers in the accumulator and register b. the low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in b. if the product is greater than 255 (0ffh) the overflow flag is set; otherwise it is cleared. the carry flag is always cleared example: originally the accumulator holds the value 80 (50h). register b holds the value 160 (0a0h). the instruction, mul ab will give the product 12,800 (3200h), so b is changed to 32h (00110010b) and the accumulator is cleared. the overflow flag is set, carry is cleared. bytes: 1 cycles: 4 encoding: 1 0 1 0 0 1 0 0 operation: mul (a) 7-0 (a)(b) (a)(b) (b) 15-8 66
nop function: no operation description: execution continues at the following instruction. other than the pc, no registers or flags are affected. example: it is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. a simple setb/clr sequence would generate a one-cycle pulse, so four additional cycles must be inserted. this may be done (assuming no interrupts are enabled) with the instruction sequence. clr p2.7 nop nop nop nop setb p2.7 bytes: 1 cycles: 1 encoding: 0 0 0 0 0 0 0 0 operation: nop (pc) (pc)+1 (pc)+1 orl , function: logical-or for byte variables description: orl performs the bitwise logical-or operation between the indicated variables, storing the results in the destination byte. no flags are affected. the two operands allow six addressing mode combinations. when the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: if the accumulator holds 0c3h (11000011b) and r0 holds 55h (01010101b) then the instruction, orl a, r0 will leave the accumulator holding the value 0d7h (11010111b). when the destination is a directly addressed byte, the instruction can set combinations of bits in any ram location or hardware register. the pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the accumulator at run-time.the instruction, orl p1, #00110010b will set bits 5,4, and 1of output port 1. 67
orl a,rn bytes: 1 cycles: 1 encoding: 0 1 0 0 1 r r r operation: orl (a) (a) (a) (a) " (rn) orl a,direct bytes: 2 cycles: 1 encoding: 0 1 0 0 0 1 0 1 direct address operation: orl (a) (a) (a) (a) " (direct) orl a,@ri bytes: 1 cycles: 1 encoding: 0 1 0 0 0 1 1 i operation: orl (a) (a) (a) (a) " ((ri)) orl a,#data bytes: 2 cycles: 1 encoding: 0 1 0 0 0 1 0 0 immediate data operation: orl (a) (a) (a) (a) " #data orl direct, a bytes: 2 cycles: 1 encoding: 0 1 0 0 0 0 1 0 direct address operation: orl (direct) (direct) (direct) (direct) " (a) orl direct, #data bytes: 3 cycles: 2 encoding: 0 1 0 0 0 0 1 1 direct address immediate data operation: orl (direct) (direct) (direct) (direct) " #data 68
orl c, function: logical-or for bit variables description: set the carry flag if the boolean value is a logical 1; leave the carry in its current state otherwise. a slash (? / ?) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. no other flags are affected. example: set the carry flag if and only if p1.0 = 1, acc. 7 = 1, or ov = 0: mov c, p1.0 ;load carry with input pin p10 orl c, acc.7 ;or carry with the acc.bit 7 orl c, /ov ;or carry with the inverse of ov orl c, bit bytes: 2 cycles: 2 encoding: 0 1 1 1 0 0 1 0 bit address operation: orl (c) (c) (c) (c) " (bit) orl c, /bit bytes: 2 cycles: 2 encoding: 1 0 1 0 0 0 0 0 bit address operation: orl (c) (c) (c) (c) " (bit) pop direct function: pop from stack description: the contents of the internal ram location addressed by the stack pointer is read, and the stack pointer is decremented by one. the value read is then transferred to the directly addressed byte indicated. no flags are affected. example: the stack pointer originally contains the value 32h, and internal ram locations 30h through 32h contain the values 20h, 23h, and 01h, respectively. the instruction sequence, pop dph pop dpl will leave the stack pointer equal to the value 30h and the data pointer set to 0123h. at this point the instruction, pop sp will leave the stack pointer set to 20h. note that in this special case the stack pointer was decremented to 2fh before being loaded with the value popped (20h). bytes: 2 cycles: 2 encoding: 1 1 0 1 0 0 0 0 direct address operation: pop (diect) ((sp)) ((sp)) (sp) (sp)-1 (sp)-1 (sp) - 1 69
push direct function: push onto stack description: the stack pointer is incremented by one. the contents of the indicated variableis then copied into the internal ram location addressed by the stack pointer. otherwise no flags are affected. example: on entering interrupt routine the stack pointer contains 09h. the data pointer holds the value 0123h. the instruction sequence, push dpl push dph will leave the stack pointer set to 0bh and store 23h and 01h in internal ram locations 0ah and 0bh, respectively. bytes: 2 cycles: 2 encoding: 1 1 0 0 0 0 0 0 direct address operation: push (sp) (sp)+1 (sp)+1 (sp) + 1 ((sp)) (direct) (direct) (direct) ret function: return from subroutine description: ret pops the high-and low-order bytes of the pc successively from the stack, decrementing the stack pointer by two. program execution continues at the resulting address, generally the instruction immediately following an acall or lcall. no flags are affected. example: the stack pointer originally contains the value 0bh. internal ram locations 0ah and 0bh contain the values 23h and 01h, respectively. the instruction, ret will leave the stack pointer equal to the value 09h. program execution will continue at location 0123h. bytes: 1 cycles: 2 encoding: 0 0 1 0 0 0 1 0 operation: ret (pc 15-8 ) ((sp)) ((sp)) ((sp)) (sp) (sp) -1 (sp) -1 (sp) -1 (pc 7-0 ) ((sp)) ((sp)) ((sp)) (sp) (sp) -1 (sp) -1 (sp) -1 70
reti function: return from interrupt description: reti pops the high- and low-order bytes of the pc successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. the stack pointer is left decremented by two. no other registers are affected; the psw is not automatically restored to its pre-interrupt status. program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. if a lower- or same-level interrupt had been pending when the reti instruction is executed, that one instruction will be executed before the pending interrupt is processed. example: the stack pointer originally contains the value 0bh. an interrupt was detected during the instruction ending at location 0122h. internal ram locations 0ah and 0bh contain the values 23h and 01h, respectively. the instruction, reti will leave the stack pointer equal to 09h and return program execution to location 0123h. bytes: 1 cycles: 2 encoding: 0 0 1 1 0 0 1 0 operation: reti (pc 15-8 ) ((sp)) ((sp)) ((sp)) (sp) (sp) -1 (sp) -1 (sp) -1 (pc 7-0 ) ((sp)) ((sp)) ((sp)) (sp) (sp) -1 (sp) -1 (sp) -1 rl a function: rotate accumulator left description: the eight bits in the accumulator are rotated one bit to the left. bit 7 is rotated into the bit 0 position. no flags are affected. example: the accumulator holds the value 0c5h (11000101b). the instruction, rl a leaves the accumulator holding the value 8bh (10001011b) with the carry unaffected. bytes: 1 cycles: 1 encoding: 0 0 1 0 0 0 1 1 operation: rl (a n +1 ) (a (a (a n ) n = 0-6 (a 0 ) (a (a (a 7 ) 71
rlc a function: rotate accumulator left through the carry flag description: the eight bits in the accumulator and the carry flag are together rotated one bit to the left. bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. no other flags are affected. example: the accumulator holds the value 0c5h (11000101b), and the carry is zero. the instruction, rlc a leaves the accumulator holding the value 8bh (10001011b) with the carry set. bytes: 1 cycles: 1 encoding: 0 0 1 1 0 0 1 1 operation: rlc (a n +1 ) (a (a (a n ) n = 0-6 (a 0 ) (c) (c) (c) (c) (a (a (a 7 ) rr a function: rotate accumulator right description: the eight bits in the accumulator are rotated one bit to the right. bit 0 is rotated into the bit 7 position. no flags are affected. example: the accumulator holds the value 0c5h (11000101b). the instruction, rr a leaves the accumulator holding the value 0e2h (11100010b) with the carry unaffected. bytes: 1 cycles: 1 encoding: 0 0 0 0 0 0 1 1 operation: rr (a n ) (a (a (a n +1) n = 0 - 6 (a 7 ) (a (a (a 0 ) rrc a function: rotate accumulator right through the carry flag description: the eight bits in the accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position.no other flags are affected. example: the accumulator holds the value 0c5h (11000101b), and the carry is zero. the instruction, rrc a leaves the accumulator holding the value 62h (01100010b) with the carry set. bytes: 1 cycles: 1 encoding: 0 0 0 1 0 0 1 1 operation: rrc (a n +1 ) (a (a (a n ) n = 0-6 (a 7 ) (c) (c) (c) (c) (a (a (a 0 ) 72
setb function: set bit description: setb sets the indicated bit to one. setb can operate on the carry flag or any directly addressable bit. no other flags are affected example: the carry flag is cleared. output port 1 has been written with the value 34h (00110100b). the instructions, setb c setb p1.0 will leave the carry flag set to 1 and change the data output on port 1 to 35h (00110101b). setb c bytes: 1 cycles: 1 encoding: 1 1 0 1 0 0 1 1 operation: setb (c) 1 1 1 setb bit bytes: 2 cycles: 1 encoding: 1 1 0 1 0 0 1 0 bit address operation: setb (bit) 1 1 1 sjmp rel function: short jump description: program control branches unconditionally to the address indicated. the branch destination is computed by adding the signed displacement in the second instruction byte to the pc, after incrementing the pc twice. therefore, the range of destinations allowed is from 128bytes preceding this instruction to 127 bytes following it. example: the label ?reladr? is assigned to an instruction at program memory location 0123h. the instruction, sjmp reladr will assemble into location 0100h. after the instruction is executed, the pc will contain the value 0123h. ( note: under the above conditions the instruction following sjmp will be at 102h.therefore, the displacement byte of the instruction will be the relative offset (0123h - 0102h) = 21h. put another way, an sjmp with a displacement of 0feh would be an one-instruction infinite loop). bytes: 2 cycles: 2 encoding: 1 0 0 0 0 0 0 0 rel. address operation: sjmp ( pc ) (pc)+2 (pc)+2 (pc)+2 (pc) (pc)+rel (pc)+rel (pc)+rel 73
subb a, function: subtract with borrow description: subb subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. subb sets the carry (borrow)flag if a borrow is needed for bit 7, and clears c otherwise.(if c was set before executing a subb instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand).ac is set if a borrow is needed for bit 3, and cleared otherwise. ov is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. when subtracting signed integers ov indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. the source operand allows four addressing modes: register, direct, register-indirect, or immediate. example: the accumulator holds 0c9h (11001001b), register 2 holds 54h (01010100b), and the carry flag is set. the instruction, subb a, r2 will leave the value 74h (01110100b) in the accumulator, with the carry flag and ac cleared but ov set. notice that 0c9h minus 54h is 75h. the difference between this and the above result is due to the carry (borrow) flag being set before the operation. if the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by a clr c instruction. subb a, rn bytes: 1 cycles: 1 encoding: 1 0 0 1 1 r r r operation: subb (a) (a) - (c) - (rn) (a) - (c) - (rn) (a) - (c) - (rn) subb a, direct bytes: 2 cycles: 1 encoding: 1 0 0 1 0 1 0 1 direct address operation: subb (a) (a) - (c) - (direct) (a) - (c) - (direct) (a) - (c) - (direct) subb a, @ri bytes: 1 cycles: 1 encoding: 1 0 0 1 0 1 1 i operation: subb (a) (a) - (c) - ((ri)) (a) - (c) - ((ri)) (a) - (c) - ((ri)) 74
swap a function: swap nibbles within the accumulator description: swap a interchanges the low- and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). the operation can also be thought of as a four-bit rotate instruction. no flags are affected. example: the accumulator holds the value 0c5h (11000101b). the instruction, swap a leaves the accumulator holding the value 5ch (01011100b). bytes: 1 cycles: 1 encoding: 1 1 0 0 0 1 0 0 operation: swap (a 3-0 ) (a 7-4 ) xch a, function: exchange accumulator with byte variable description: xch loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. the source/destination operand can use register, direct, or register-indirect addressing. example: r0 contains the address 20h. the accumulator holds the value 3fh (001 1111 1b). internal ram location 20h holds the value 75h (01110101b). the instruction, xch a, @r0 will leave ram location 20h holding the values 3fh (001 1111 1b) and 75h (01110101b) in the accumulator. xch a, rn bytes: 1 cycles: 1 encoding: 1 1 0 0 1 r r r operation: xch (a) (rn) xch a, direct bytes: 2 cycles: 1 encoding: 1 1 0 0 0 1 0 1 direct address operation: xch (a) (direct) subb a, #data bytes: 2 cycles: 1 encoding: 1 0 0 1 0 1 0 0 immediate data operation: subb (a) (a) - (c) - #data (a) - (c) - #data (a) - (c) - #data 75
xch a, @ri bytes: 1 cycles: 1 encoding: 1 1 0 0 0 1 1 i operation: xch (a) ((ri)) xchd a, @ri function: exchange digit description: xchd exchanges the low-order nibble of the accumulator (bits 3-0), generally representing a hexadecimal or bcd digit, with that of the internal ram location indirectly addressed by the specified register. the high-order nibbles (bits 7-4) of each register are not affected. no flags are affected. example: r0 contains the address 20h. the accumulator holds the value 36h (00110110b). internal ram location 20h holds the value 75h (01110101b). the instruction, xchd a, @r0 will leave ram location 20h holding the value 76h (01110110b) and 35h (00110101b) in the accumulator. bytes: 1 cycles: 1 encoding: 1 1 0 1 0 1 1 i operation: xchd (a 3-0 ) (ri 3-0 ) xrl , function: logical exclusive-or for byte variables description: xrl performs the bitwise logical exclusive-or operation between the indicated variables, storing the results in the destination. no flags are affected. the two operands allow six addressing mode combinations.when the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address,the source can be the accumulator or immediate data. ( note : when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.) example: if the accumulator holds 0c3h (11000011b) and register 0 holds 0aah (10101010b) then the instruction, xrl a, r0 will leave the accumulator holding the vatue 69h (01101001b). when the destination is a directly addressed byte, this instruction can complement combinna- tion of bits in any ram location or hardware register. the pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the accumulator at run-time. the instruction, xrl p1, #00110001b will complement bits 5,4 and 0 of outpue port 1. 76
xrl a, rn bytes: 1 cycles: 1 encoding: 0 1 1 0 1 r r r operation: xrl (a) (a) (a) (rn) xrl a, direct bytes: 2 cycles: 1 encoding: 0 1 1 0 0 1 0 1 direct address operation: xrl (a) (a) (a) (direct) xrl a, @ri bytes: 1 cycles: 1 encoding: 0 1 1 0 0 1 1 i operation: xrl (a) (a) (a) ((ri)) xrl a, #data bytes: 2 cycles: 1 encoding: 0 1 1 0 0 1 0 0 immediate data operation: xrl (a) (a) (a) #data xrl direct, a bytes: 2 cycles: 1 encoding: 0 1 1 0 0 0 1 0 direct address operation: xrl (direct) (direct) (direct) (a) xrl direct, #dataw bytes: 3 cycles: 2 encoding: 0 1 1 0 0 0 1 1 direct address immediate data operation: xrl (direct) (direct) (direct) # data 77
there are 8 interrupt vector addresses available in stc89xx series. associating with each interrupt vector, each interrupt source can be individually enabled or disabled by setting or clearing a bit in the registers ie and xicon. the register also contains a global disable bit(ea), which can be cleared to disable all interrupts at once. each interrupt source has two corresponding bits to represent its priority. one is located in sfr named iph and the other in ip or xicon register. higher-priority interrupt will be not interrupted by lower-priority interrupt request. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine which request is serviced. the following table shows the internal polling sequence in the same priority level and the interrupt vector address. chapter 6 interrupt interrupt source vector address polling sequence interrupt priority setting (ip/xicon,iph) priority 0 (lowest) priority 1 priority 2 priority 3 (highest) interrupt request interrupt enable control bit /int0 (external interrupt 0) 0003h 0(highest) px0h,px0 0,0 0,1 1,0 1,1 ie0 ex0/ea timer 0 000bh 1 pt0h,pt0 0,0 0,1 1,0 1,1 tf0 et0/ea /int1 (external interrupt 1) 0013h 2 px1h,px1 0,0 0,1 1,0 1,1 ie1 ex1/ea timer1 001bh 3 pt1h,pt1 0,0 0,1 1,0 1,1 tf1 et1/ea uart (serial interface) 0023h 4 psh,ps 0,0 0,1 1,0 1,1 ri+ti es/ea timer 2 002bh 5 pt2h,pt2 0,0 0,1 1,0 1,1 tf2+exf2 et2/ea /int2 0033h 6 px2h,px2 0,0 0,1 1,0 1,1 ie2 ex2/ea /int3 003bh 7(lowest) px3h,px3 0,0 0,1 1,0 1,1 ie3 ex3/ea 78
6.1 interrupt structure interrupt system diagram of stc89xx series highest priority level interrupt ip,xicon,iph registers ie, xicon registers ex2 ex3 global enable ea /int0 tf0 /int1 tf1 ri ti tf2+exf2 ie0 ie1 et2 es et1 ex1 et0 ex0 lowest priority level interrupt interrupt polling sequence high low tcon.0/it0=1 tcon.0/it0=0 tcon.2/it1=1 tcon.2/it1=0 ea /int2 ie2 xicon.0/it2=1 xicon.0/it2=0 /int3 ie2 xicon.4/it3=1 xicon.4/it3=0 79
the external interrupts int0 , int1 , int2 and int3 can each be either level-activated or transition-activated, depending on bits it0 and it1 in register tcon, it2 and it3 in sfr xicon. the flags that actually generate these interrupts are bits ie0 and ie1 in tcon, ie2 and ie3 in xicon. when an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to if and only if the interrupt was transition ?activated, otherwise the external requesting source is what controls the request flag, rather than the on-chip hardware. the timer 0 and timer1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers in most cases. when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. the serial port interrupt is generated by the logical or of ri and ti. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine will normally have to determine whether it was ri and ti that generated the interrupt, and the bit will have to be cleared by software. the timer 2 interrupt is generates by the logical or of tf2 and exf2. just the same as serial port, neither of these flags is cleared by hardware when the service routine is vectored to. all of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. in other words, interrupts can be generated or pending interrupts can be canceled in software. 6.2 interrupt register symbol description address bit address and symbol msb lsb value after power-on or reset ie interrupt enable a8h ea - et2 es et1 ex1 et0 ex0 0000 0000b ip interrupt priority low b8h - - pt2 ps pt1 px1 pt0 px0 xx00 0000b iph interrupt priority high b7h px3h px2h pt2h psh pt1h px1h pt0h px0h 0000,0000b tcon timer/counter 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0000 0000b scon serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 0000 0000b t2con timer/counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 0000 0000b xicon auxiliary interupt control c0h px3 ex3 ie3 it3 px2 ex2 ie2 it1 0000 0000b 80
ie: interrupt enable rsgister ea - et2 es et1 ex1 et0 ex0 (msb) (lsb) enable bit = 1 enables the interrupt . enable bit = 0 disables it . symbol position function ea ie.7 disables all interrupts. if ea = 0,no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. et2 ie.5 timer 2 interrupt enable bit es ie.4 serial port interrupt enable bit et1 ie.3 timer 1 interrupt enable bit ex1 ie.2 external interrupt 1 enable bit et0 ie.1 timer 0 interrupt enable bit ex0 ie.0 external interrupt 0 enable bit ip: interrupt priority low register - - pt2 ps pt1 px1 pt0 px0 (msb) (lsb) priority bit = 1 assigns high priority . priority bit = 0 assigns low priority. symbol position function pt2 ip.5 timer 2 interrupt priority bit ps ip.4 serial port interrupt priority bit. pt1 ip.3 timer 1 interrupt priority bit px1 ip.2 external interrupt 1 priority bit pt0 ip.1 timer 0 interrupt priority bit px0 ip.0 external interrupt 0 priority bit iph: interrupt priority high register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name px3h px2h pt2h psh pt1h px1h pt0h px0h px3h : if set, set priority for external interrupt 3 highest px2h : if set, set priority for external interrupt 2 highest pt2h : if set, set for timer 2 interrupt highest psh : if set, set priority for serial port highest pt1h : if set, set priority for timer 1 interrupt highest px1h : if set, set priority for external interrupt 1 highest pt0h : if set, set priority for timer 0 interrupt highest px0h : if set, set priority for external interrupt 0 highest 81
tcon register : timer/counter control register tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 (msb) (lsb) symbol position name and significance symbol position name and significance tf1 tcon.7 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. ie1 tcon.3 interrupt 1 edge flag. set by hardware when external interrupt edge detected.cleared when interrupt processed. tr1 tcon.6 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. it1 tcon.2 intenupt 1 type control bit. set/ cleared by software to specify falling edge/low level triggered external interrupts. tf0 tcon.5 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. ie0 tcon.1 interrupt 0 edge flag. set by hardware when external interrupt edge detected.cleared when interrupt processed. tr0 tcon.4 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. it0 tcon.0 intenupt 0 type control bit. set/ cleared by software to specify falling edge/low level triggered external interrupts. scon register lsb bit 7654321 0 name sm0/fe sm1 sm2 ren tb8 rb8 ti ri fe: framing error bit. the smod0 bit must be set to enable access to the fe bit 0: the fe bit is not cleared by valid frames but should be cleared by software. 1: this bit set by the receiver when an invalid stop bit id detected. sm0,sm1 : serial port mode bit 0/1. sm0 sm1 description baud rate 0 0 8-bit shift register sysclk/12 0 1 8-bit uart variable 1 0 9-bit uart sysclk/64 or sysclk/32(smod=1) 1 1 9-bit uart variable sm2 : enable the automatic address recognition feature in mode 2 and 3. if sm2=1, ri will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast address. in mode1, if sm2=1 then ri will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren : when set enables serial reception. tb8 : the 9th data bit which will be transmitted in mode 2 and 3. rb8 : in mode 2 and 3, the received 9th data bit will go into this bit. ti : transmit interrupt flag. ri : receive interrupt flag. 82
t2con: timer/counter 2 control register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 tf2 : timer 2 overflow flag. tf2 is set by a timer 2 overflow happens and must be cleared by software. tf2 will not be set when either rclk=1 or tclk=1. exf2 : timer 2 external flag. timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex(p1.1) pin and exen2=1. when timer 2 interrupt is enabled, exf2=1 will cause the cpu to vector the timer 2 interrupt routine. exf2 must be cleared by software.exf2 does not cause an interrupt in up/down mode(dcen=1). rclk : receive clock flag. when set, cause the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. when cleared, cause timer 1 overflow to be used for the receive clock. tclk : transmit clock flag.when set, cause the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. when cleared, cause timer 1 overflows to be used for the transmit clock. exen2 : timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex(p1.1) pin if timer 2 is not being used to clock the serial port. when cleared, cause timer 2 to ignore events at t2ex(p1.1) pin. tr2 : timer 2 run control bit.when set, start the timer 2. when cleared, stop the timer 2. c/t2 : timer or counter selector. 0: select timer 2 as internal timer function. 1: select timer 2 as external event counter (falling edge triggered). cp/rl2 : capture/reload flag. 0 : auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex pin when exen2=1. 1 : captures will occur on negative transitions at t2ex pin if exen2=1. xicon: auxiliary interrupt control register lsb bitb7b6b5b4b3b2b1b0 name px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3 : if set, set priority for external interrupt 3 higher ex3 : if set, enables external interrupt 3. ie3 : external interrupt 3 edge flag. sets by hardware when external interrupt edge detected.cleared by hardware when interrupt is starting to be serviced. it3 : external interrupt 3 type control bit. set/cleared by software to specified falling edge/low level triggered interrupt. px2 : if set, set priority for external interrupt 3 higher ex2 : if set, enables external interrupt 2. ie2 : external interrupt 2 edge flag. sets by hardware when external interrupt edge detected. cleared when interrupt is starting to be serviced. it2 : interrupt 2 types control bit. set/cleared by software to specify falling edge/low level triggered interrupt. ip (or xicon) and iph are combined to form 4-level priority interrupt as the following table. {iph.x, ip.x/xicon.x} priority level 1,1 0(highest) 1,0 1 0,1 2 0,0 3 83
6.4 how interrupts are handled each interrupt flag is sampled at every system clock cycle. the samples are polled during the next system clock. if one of the flags was in a set condition at first cycle, the second cycle(polling cycle) will find it and the interrupt system will generate an hardware lcall to the appropriate service routine as long as it is not blocked by any of the following conditions. block conditions : an interrupt of equal or higher priority level is already in progress. the current cycle(polling cycle) is not the final cycle in the execution of the instruction in progress. the instruction in progress is reti or any write to the ie or ip registers. the isp/iap activity is in progress. any of these four conditions will block the generation of the hardware lcall to the interrupt service routine. condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine. condition 3 ensures that if the instruction in progress is reti or any access to ie or ip, then at least one or more instruction will be executed before any interrupt is vectored to. the polling cycle is repeated with the last clock cycle of each instruction cycle. note that if an interrupt flag is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. the interrupt flag was once active but not serviced is not kept in memory. every polling cycle is new. ? ? ? ? 6.3 interrupt priorities each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in special function registers ip or xicon and iph . a low-priority interrupt can itself be interrupted by a high-pority interrupt, but not by another low-priority interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence,as follows: source priority within level 0. ie0 0(highest) 1. tf0 1 2. ie1 2 3. tf1 3 4. ri +tl 4 5. tf2+exf2 5 6. ie2 6 7. ie3 7 note that the ?priority within level? structure is only used to resolve simultaneous requests of the same prionty level. 84
note that if an interrupt of higher priority level goes active prior to rising edge of the third machine cycle, then in accordance with the above rules it will be vectored to during the fifth and sixth machine cycle, without any instruction of the lower priority routine having been executed. thus the processor acknowledges an interrupt request by executing a hardware-generated lcall to the appropriate servicing routine. in some cases it also clears the flag that generated the interrupt, and in other cases it doesn?t. it never clears the serial port flags. this has to be done in the user?s software. it clears an external interrupt flag (ie0 or ie1) only if it was transition-activated. the hardware-generated lcall pushes the contents of the program counter onto the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to, as shown be low. source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri+ti 0023h tf2+exf2 002bh ie2 0033h ie3 003bh execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it left off. note that a simple ret instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. 6.5 external interrupts there are four external interrupt sources in stc89xx mcu. the external sources can be programmed to be level- activated or transition-activated by clearing or setting bits it0, it1, it2 or it3 in registers tcon or xicon. if itx=0, external interrupt x is triggered by a detected low at the intx pin. if itx=1, external interrupt x is edge- triggered. in this mode if successive samples of the intx pin show a high in one cycle and a low in the next cycle, interrupt request flag iex in tcon is set. flag bit iex then requests the interrupt. since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 system clocks to ensure sampling. if the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag iex will be set. iex will be automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. 85
example : design an intrusion warning system using interrupts that sounds a 400hz tone for 1 second (using a loudspeaker connected to p1.7) whenever a door sensor connected to int0 makes a high-to-low transition. assembly language solution org 0 ljmp main ;3-byte instruction ljmp int0int ;ext 0 vector address org 000bh ;timer 0 vector ljmp t0int org 001bh ;timer 1 vector ljmp t1int org 0030h main: setb it0 ;negative edge activated mov tmod, #11h ;16-bit timer mode mov ie, #81h ;enable ext 0 only sjmp $ ;now relax ; int0int: mov r7, #20 ;20 ' 5000 us = 1 second setb tf0 ;force timer 0 interrupt setb tf1 ;force timer 1 interrupt setb et0 ;begin tone for 1 second setb et1 ;enable timer interrupts reti ; t0int: clr tr0 ;stop timer djnz r7, skip ;if not 20th time, exit clr et0 ;if 20th, disable tone clr et1 ;disable itself ljmp exit skip: mov th0, #high (-50000) ;0.05sec. delay mov tl0, #low (-5000) setb tr0 exit: reti ; t1int: clr tr1 mov th1, #high (-1250) ;count for 400hz mov tl1, #low (-1250) cpl p1.7 ;music maestro! setb tr1 reti end 86
c language solution #include /* sfr declarations */ sbit outbit = p1^7; /* use variable outbit to refer to p1.7 */ unsigned char r7; /* use 8-bit variable to represent r7 */ main( ) { it0 = 1; /* negative edge activated */ tmod = 0x11; /* 16-bit timer mode */ ie = 0x81; /* enable ext 0 only */ while(1); } void int0int(void) interrupt 0 { r7 = 20; /* 20 x 5000us = 1 second */ tf0 = 1; /* force timer 0 interrupt */ tf1 = 1; /* force timer 1 interrupt */ et0 = 1; /* begin tone for 1 second */ et1 = 1; /* enable timer 1 interrupts */ /* timer interrupts will do the work */ } void t0int(void) interrupt 1 { tr0 = 0; /* stop timer */ r7 = r7-1; /* decrement r7 */ if (r7 == 0) /* if 20 th time, */ { et0 = 0; /* disable itself */ et1 = 0; } else { th0 = 0x3c; /* 0.05 sec. delay */ tl0 = 0xb0; } } void t1int (void) interrupt 3 { tr0 = 0; th1 = 0xfb; /* count for 400hz */ tl1 = 0x1e; outbit = !outbit; /* music maestro! */ tr1 = 1; } 87
6.6 response time the int0 , int1 , int2 and int3 levels are inverted and latched into the interrupt flags ie0, ie1, ie2 and ie3 at rising edge of every syetem clock cycle. the timer 0 and timer 1 flags, tf0 and tf1, are set after which the timers overflow. the values are then polled by the circuitry at rising edge of the next system clock cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the call itself takes six system clock cycles. thus, a minimum of seven complete system clock cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. a longer response time would result if the request is blocked by one of the four previously listed conditions. if an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt?s service routine. if the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (lcall) are only 6 cycles long, and if the instruction in progress is reti or an access to ie or ip, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 6 cycles to complete the next instruction if the instruction is lcall). thus, in a single-interrupt system, the response time is always more than 7 cycles and less than 12 cycles. in the above assembly language solution, five distinct sections are the interrupt vector loactions, the main program, and the three interrupt service routines. all vector loacations contain ljmp instructions to the respective routines. the main program, starting at code address 0030h, contains only four instructions. setb it0 configures the door sensing interrupt input as negative-edge triggered. mov tmod, #11h configures both timers for mode 1, 16-bit timer mode. only the external 0 interrupt is enabled initially (mov ie,#81h), so a "door-open" condition is needed before any interrupt is accepted. finally, sjmp $ puts the main program in a do-nothing loop. when a door-open condition is sensed (by a high-to-low transition of int0), an external 0 interrupt is generated, int0int begins by putting the constant 20 in r7, then sets the overflow flags for both timers to force timer interrupts to occur. timer interrupt will only occur, however, if the respective bits are enabled in the ie register. the next two instructions (setb et0 and setb et1) enable timer interrupts. finally, int0int terminates with a reti to the main program. timer 0 creates the 1 second timeout, and timer 1 creates the 400hz tone. after int0int returns to the main program, timer interrupt are immediately generated (and accepted after one excution of sjmp $). because of the fixed polling sequence, the timer 0 interrupt is serviced first. a 1 second timeout is created by programming 20 repetitions of a 50,000 us timeout. r7 serves as the counter. nineteen times out of 20, t0int operates as follows. first, timer 0 is turned off and r7 is decremented. then, th0/tl is reload with -50,000, the timer is turned back on, and the interrupt is terminated. on the 20th timer 0 interrupt, r7 is decremented to 0 (1 second has elapsed). both timer interrupts are disabled(clr et0, clr et1)and the interrupt is terminated. no further timer interrupts will be generated until the next "door-open" condition is sensed. the 400hz tone is programmed using timer 1 interrupts, 400hz requires a period of 1/400 = 2,500 us or 1,250 high-time and 1,250 us low-time. each timer 1 isr simply puts -1250 in th1/tl1, complements the port bit driving the loudspeaker, then terminates. 88
chapter 7 timer/counter stc89xx has three 16-bit timers, and they are named t0, t1 and t2. each of them can also be individually configured as timers or event counters. in the ?timer? function, the register is incremented every 12 system clocks or 6 system clocks depending on 12t mode or 6t mode that the user configured this device. in the ?counter? function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0,t1 or t2. in this function, the external input is sampled once at the positive edge of every clock cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register at the end of the cycle following the one in which the transition was detected. since it takes 2 machine cycles(24 system clocks) to recognize a l-to-0 transition, the maximum count rate is 1/24 of the system clock. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. the ?timer? or ?counter? function of timer 0 and timer 1 is selected by control bits c/t in the speciai function register tmod. and the ?timer? or ?counter? function of timer 2 is selected by control bit c/t2 in the speciai function register t2con. there are two sfr designed to configure timers t0 and t1. they are tmod, tcon. there are extra two sfr designed to configure timer t2. they are t2mod, t2con. symbol description address bit address and symbol msb lsb value after power-on or reset tcon timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 0000 0000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 0000 0000b tl0 timer low 0 8ah 0000 0000b tl1 timer low 1 8bh 0000 0000b th0 timer high 0 8ch 0000 0000b th1 timer high 1 8dh 0000 0000b t2con timer/counter 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 0000 0000b t2mod timer/counter 2 mode c9h ------t2oedcen xxxx xx00b rcap2l timer/counter 2 reload/ capture high byte cah 0000 0000b rcap2h timer/counter 2 reload/ capture high byte cbh 0000 0000b tl2 timer/counter 2 low byte cch 0000 0000b th2 timer/counter 2 high byte cdh 0000 0000b 89
tmod register : timer/counter mode control register gate c/t m1 m0 gate c/t m1 m0 (msb) (lsb) } } timer 1 timer 0 gate gating control when set. timer/counter "x" is enabled only while " intx " pin is high and "trx"control pin is set.when cleared timer "x" is enabled whenever "trx" control bit is set. c/t timer or counter selector cleared for timer operation (input from internal system clock). set for counter operation (input from "tx" input pin). m0 m1 operating mode 00 b-bit timer/counter "thx" with "tlx" as 5-bit prescaler. 01 16-bit timer/counter"thx"and"tlx"are cascaded;there is no prescaler 10 8-bit auto-reload timer/counter ?thx? holds a value which is to be reloaded into ?tlx? each time it overflows. 11 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits th0 is an 8-bit timer only controlled by timer 1 control bits. 11 (timer 1) timer/counter 1 stopped tcon register : timer/counter control register tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 (msb) (lsb) symbol position name and significance symbol position name and significance tf1 tcon.7 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. ie1 tcon.3 interrupt 1 edge flag. set by hardware when external interrupt edge detected.cleared when interrupt processed. tr1 tcon.6 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. it1 tcon.2 intenupt 1 type control bit. set/ cleared by software to specify falling edge/low level triggered external interrupts. tf0 tcon.5 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. ie0 tcon.1 interrupt 0 edge flag. set by hardware when external interrupt edge detected.cleared when interrupt processed. tr0 tcon.4 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. it0 tcon.0 intenupt 0 type control bit. set/ cleared by software to specify falling edge/low level triggered external interrupts. 90
t2con: timer/counter 2 control register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 tf2 : timer 2 overflow flag. tf2 is set by a timer 2 overflow happens and must be cleared by software. tf2 will not be set when either rclk=1 or tclk=1. exf2 : timer 2 external flag. timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex(p1.1) pin and exen2=1. when timer 2 interrupt is enabled, exf2=1 will cause the cpu to vector the timer 2 interrupt routine. exf2 must be cleared by software.exf2 does not cause an interrupt in up/down mode(dcen=1). rclk : receive clock flag. when set, cause the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. when cleared, cause timer 1 overflow to be used for the receive clock. tclk : transmit clock flag.when set, cause the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. when cleared, cause timer 1 overflows to be used for the transmit clock. exen2 : timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex(p1.1) pin if timer 2 is not being used to clock the serial port. when cleared, cause timer 2 to ignore events at t2ex(p1.1) pin. tr2 : timer 2 run control bit.when set, start the timer 2. when cleared, stop the timer 2. c/t2 : timer or counter selector. 0: select timer 2 as internal timer function. 1: select timer 2 as external event counter (falling edge triggered). cp/rl2 : capture/reload flag. 0 : auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex pin when exen2=1. 1 : captures will occur on negative transitions at t2ex pin if exen2=1. t2mod: timer/counter 2 mode register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name ------t20edcen t2oe : timer 2 output enable bit. it enables timer 2 overflow rate to toggle p1.0. dcen: down count enable bit. when set, this allows timer 2 to be configured as down counter 91
interrupt sysclk tl0 (5 bits) th0 (8 bits) tf0 control c/t=0 c/t=1 t0 pin tr0 gate int0 12 6 mcu in 6t mode timer/counter 0 mode 0: 13-bit counter mcu in 12t mode mode 1 in this mode, the timer register is configured as a 16-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf0. the counted input is enabled to the timer when tr0 = 1 and either gate=0 or int0 = 1.(setting gate = 1 allows the timer to be controlled by external input int0 , to facilitate pulse width measurements.) tr0 is a control bit in the special function register tcon. gate is in tmod. the 16-bit register consists of all 8 bits of th0 and the lower 8 bits of tl0. setting the run flag (tr0) does not clear the registers. mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. interrupt sysclk tl0 (8 bits) th0 (8 bits) tf0 control c/t=0 c/t=1 t0 pin tr0 gate int0 mcu in 12t mode 12 6 mcu in 12t mode timer/counter 0 mode 1 : 16-bit counter mode 0 in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf0. the counted input is enabled to the timer when tr0 = 1 and either gate=0 or int0 = 1.(setting gate = 1 allows the timer to be controlled by external input int0 , to facilitate pulse width measurements.) tr0 is a control bit in the special function register tcon. gate is in tmod. the 13-bit register consists of all 8 bits of th0 and the lower 5 bits of tl0. the upper 3 bits of tl0 are indeterminate and should be ignored. setting the run flag (tr0) does not clear the registers. there are two different gate bits. one for timer 1 (tmod.7) and one for timer 0 (tmod.3). 7.1 timer/counter 0 mode of operation 92
mode 3 timer 1 in mode 3 simply holds its count, the effect is the same as setting tr1 = 0. timer 0 in mode 3 established tl0 and th0 as two separate 8-bit counters. tl0 use the timer 0 control bits: c/t ,gate,tr0, int0 and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 from tmer 1. thus, th0 now controls the ?timer 1? interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. interrupt sysclk tf0 control c/t=0 c/t=1 t0 pin tr0 gate int0 mcu in 12t mode mcu in 6t mode tl0 (8 bit) control th0 (8 bits) tf1 interrupt tr1 timer/counter 0 mode 3: two 8-bit counters 12 6 sysclk 12 6 mcu in 12t mode mcu in 6t mode mode 2 mode 2 configures the timer register as an 8-bit counter(tl0) with automatic reload. overflow from tl0 not only set tf0, but also reload tl0 with the content of th0, which is preset by software. the reload leaves th0 unchanged. mode 2 operation is the same for timer 0 and timer 1. sysclk control c/t=0 c/t=1 t0 pin tr0 gate int0 mcu in 12t mode mcu in 6t mode tl0 (8 bits) th0 (8 bits) timer/counter 0 mode 2: 8-bit auto-reload 12 6 interrupt tf0 93
example: write a program using timer 0 to create a 5khz square wave on p1.0. assembly language solution : org 0030h mov tmod, #20h ;8-bit auto-reload mode mov tl0, #9ch ;initialize tl0 mov th0, #9ch ;-100 reload value in th0 setb tr0 ;start tmier 0 loop: jnb tf0, loop ;wait for overflow clr tf0 ;clear timer overflow flag cpl p1.0 ;toggle port bit sjmp loop ;repeat end c language solution using timer interrupt : #include /* sfr declarations */ sbit portbit = p1^0; /* use variable portbit to refer to p1.0 */ main( ) { tmod = 0x02; /* timer 0, mode 2 */ th0 = 9ch; /* 100us delay */ tr0 = 1; /* start timer */ ie = 0x82 /* enable timer 0 interrupt */ while(1); /* repeat forever */ } void t0int(void) interrupt 1 { portbit = !portbit; /*toggle port bit p1.0 */ } 94
7.2 timer/counter 1 mode of operation mode 0 in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf1. the counted input is enabled to the timer when tr1 = 1 and either gate=0 or int1 = 1.(setting gate = 1 allows the timer to be controlled by external input int1 , to facilitate pulse width measurements.) tr0 is a control bit in the special function register tcon. gate is in tmod. the 13-bit register consists of all 8 bits of th1 and the lower 5 bits of tl1. the upper 3 bits of tl1 are indeterminate and should be ignored. setting the run flag (tr1) does not clear the registers. mode 1 in this mode, the timer register is configured as a 16-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tf1. the counted input is enabled to the timer when tr1 = 1 and either gate=0 or int1 = 1.(setting gate = 1 allows the timer to be controlled by external input int1 , to facilitate pulse width measurements.) trl is a control bit in the special function register tcon. gate is in tmod. the 16-bit register consists of all 8 bits of thl and the lower 8 bits of tl1. setting the run flag (tr1) does not clear the registers. mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. interrupt sysclk tl1 (8 bits) th1 (8 bits) tf1 control c/t=0 c/t=1 t1 pin tr1 gate int1 mcu in 12t mode 12 6 mcu in 6t mode timer/counter 1 mode 1 : 16-bit counter interrupt sysclk tl1 (5 bits) th1 (8 bits) tf1 control c/t=0 c/t=1 t1 pin tr1 gate int1 mcu in 12t mode 12 6 mcu in 6t mode timer/counter 1 mode 0: 13-bit counter 95
example : write a program using timer 1 to create a 500hz square wave on p1.0. assembly language solution : org 0030h mov tmod, #10h ;16-bit timer mode mov th1, #0f8h ;-1000 (high byte) mov th1, #30h ;-1000 (low byte) setb tr1 ;start tmier 1 loop: jnb tf1, loop ;wait for overflow clr tf1 ;clear timer overflow flag cpl p1.0 ;toggle port bit sjmp loop ;repeat end c language solution : #include /* sfr declarations */ sbit portbit = p1^0; /* use variable portbit to refer to p1.0 */ main( ) { tmod = 0x10; /* timer 1, mode 1, 16-bit timer mode */ while (1) /* repeat forever */ { th1 = 0xf8; /* -1000 (high byte) */ tl1 = 0x30; /* -1000 (low byte) */ tr1 = 1; /* start timer 1 */ while (tf0 !=1); /* wait for overflow */ tr1 = 0; /* stop timer 1 */ tf0 = 0; /* clear timer overflow flag */ portbit = !(portbit); /* toggle p1.0 */ } } mode 2 mode 2 configures the timer register as an 8-bit counter(tl1) with automatic reload. overflow from tl1 not only set tfx, but also reload tl1 with the content of th1, which is preset by software. the reload leaves th1 unchanged. interrupt sysclk tf1 control c/t=0 c/t=1 t1 pin tr1 gate int1 mcu in 12t mode mcu in 6t mode tl1 (8 bits) th1 (8 bits) timer/counter 1 mode 2: 8-bit auto-reload 12 6 96
the following program is a assembly language code that domestrates timer 1 of stc89xx series mcu acted as baud rate generator. ;/*------------------------------------------------------------------------------------------------------------*/ ;/* --- stc mcu international limited ----------------------------------------------------------------*/ ;/* --- stc 89xx series mcu timer 1 acted as baud rate generoter demo ------------------------*/ ;/* if you want to use the program or the program referenced in the */ ;/* article, please specify in which data and procedures from stc */ ;/*--------------------------------------------------------------------------------------------------------------*/ ;declare stc89xx series mcu sfr auxr equ 8eh ;*/--------------------------------------------------------------------------------------------------------------*/ ;define baud rate auto-reload counter ;**************************************************************************** ;the following reload-count and baud is based on sysclk =22.1184mhz, 1t mode, smod=1 ;reload_count equ 0ffh ;baud=1,382,400 bps ;reload_count equ 0feh ;baud=691,200 bps ;reload_count equ 0fdh ;baud=460,800 bps ;reload_count equ 0fch ;baud=345,600 bps ;reload_count equ 0fbh ;baud=276,480 bps ;reload_count equ 0fah ;baud=230,400 bps ;reload_count equ 0f4h ;baud=115,200 bps ;reload_count equ 0e8h ;baud=57,600 bps ;reload_count equ 0dch ;baud=38,400 bps ;reload_count equ 0b8h ;baud=19,200 bps ;reload_count equ 70h ;baud=9,600 bps ;******************************************************************************* ;the following reload-count and baud is based on sysclk =1.8432mhz, 1t mode, smod=1 ;reload_count equ 0ffh ;baud=115,200 bps ;reload_count equ 0feh ;baud=57,600 bps ;reload_count equ 0fdh ;baud=38,400 bps ;reload_count equ 0fch ;baud=28,800 bps ;reload_count equ 0fah ;baud=19,200 bps ;reload_count equ 0f4h ;baud=9,600 bps ;reload_count equ 0e8h ;baud=4,800 bps ;reload_count equ 0d0h ;baud=2,400 bps ;reload_count equ 0a0h ;baud=1,200 bps ;******************************************************************************** ;the following reload-count and baud is based on sysclk =18.432mhz, 1t mode, smod=1 ;reload_count equ 0ffh ;baud=1,152,000 bps ;reload_count equ 0feh ;baud=576,000 bps ;reload_count equ 0fdh ;baud=288,000 bps ;reload_count equ 0fch ;baud=144,000 bps ;reload_count equ 0f6h ;baud=115,200 bps ;reload_count equ 0ech ;baud=57,600 bps 97
;reload_count equ 0e2h ;baud=38,400 bps ;reload_count equ 0d8h ;baud=28,800 bps ;reload_count equ 0c4h ;baud=19,200 bps ;reload_count equ 088h ;baud=9,600 bps ;******************************************************************************** ;the following reload-count and baud is based on sysclk =18.432mhz, 1t mode, smod=0 ;reload_count equ 0ffh ;baud=576,000 bps ;reload_count equ 0feh ;baud=288,000 bps ;reload_count equ 0fdh ;baud=144,000 bps ;reload_count equ 0fch ;baud=115,200 bps ;reload_count equ 0f6h ;baud=57,600 bps ;reload_count equ 0ech ;baud=38,400 bps ;reload_count equ 0e2h ;baud=28,800 bps ;reload_count equ 0d8h ;baud=19,200 bps ;reload_count equ 0c4h ;baud=96,000 bps ;reload_count equ 088h ;baud=4,800 bps ;********************************************************************************* ;the following reload-count and baud is based on sysclk =18.432mhz, 12t mode, smod=0 reload_count equ 0fbh ;baud=9,600 bps ;reload_count equ 0f6h ;baud=4,800 bps ;reload_count equ 0ech ;baud=2,400 bps ;reload_count equ 0d8h ;baud=1,200 bps ;********************************************************************************* ;the following reload-count and baud is based on sysclk =18.432mhz, 12t mode, smod=1 reload_count equ 0fbh ;baud=19,200 bps ;reload_count equ 0f6h ;baud=9,600 bps ;reload_count equ 0ech ;baud=4,800 bps ;reload_count equ 0d8h ;baud=2,400 bps ;reload_count equ 0b0h ;baud=1,200 bps ;******************************************************************************** ;the following reload-count and baud is based on sysclk =11.0592mhz, 12t mode, smod=0 ;reload_count equ 0ffh ;baud=28,800 bps ;reload_count equ 0feh ;baud=14,400 bps ;reload_count equ 0fdh ;baud=9,600 bps ;reload_count equ 0fah ;baud=4,800 bps ;reload_count equ 0f4h ;baud=2,400 bpss ;reload_count equ 0e8h ;baud=1,200 bps ;******************************************************************************** ;******************************************************************************** ;the following reload-count and baud is based on sysclk =11.0592mhz, 12t mode, smod=1 ;reload_count equ 0ffh ;baud=57,600 bps ;reload_count equ 0feh ;baud=28,800 bps ;reload_count equ 0fdh ;baud=14,400 bps ;reload_count equ 0fah ;baud=9,600 bps ;reload_count equ 0f4h ;baud=4,800 bps ;reload_count equ 0e8h ;baud=2,400 bps ;reload_count equ 0d0h ;baud=1,200 bps ;******************************************************************************** 98
;define led indicator led_mcu_start equ p1.7 ;mcu operating led indicator ;------------------------------------------------------------------------------------------------------------------------- org 0000h ajmp main ;------------------------------------------------------------------------------------------------------------------------- org 0023h ajmp uart_interrupt ;jump into rs232 uart-interrupt service subroutine nop nop ;-------------------------------------------------------------------------------------------------------------------------- main: mov sp, #7fh ;set stack pointer clr led_mcu_start ;turn on mcu operating led indicator acall initial_uart ;initialize uart mov r0, #30h ;30h = the ascii code of printable character '0' mov r2, #10 ;send ten characters '0123456789' loop: mov a, r0 acall send_one_byte ;send one byte ; if character-display, display '0123456789' ;if hexadecimal-display, display '30 31 32 33 34 35 36 37 38 39' inc r0 djnz r2, loop main_wait: sjmp main_wait ;infinite circle ;---------------------------------------------------------------------------------------------------------------------------- uart_interrupt: ;uart-interrupt service subroutine jb ri, is_uart_receive clr ti ;clear serial port transmit interrupt flag reti is_uart_receive: clr ri push acc mov a, sbuf ;acquire the received byte acall send_one_byte ;re-send the received byte pop acc reti ;----------------------------------------------------------------------------------------------------------------------- initial_uart: ;initialize uart ;scon bit: 7 6 5 4 3 2 1 0 ; sm0/fe sm1 sm2 ren tb8 rb8 ti ri mov scon, #50h ;0101,0000 8-bit variable baud rate,no odd parity bit mov tmod, #21h ;use timer 1 as 8 bit auto-reload counter mov th1, #reload_count ;set auto-reload count of timer 1 mov tl1, #reload_count ;---------------------------------------------------------------------------------------------------------------------- ; orl pcon, #80h ;baud rate double 99
;---------------------------------------------------------------------------------------------------------------------- ; orl auxr, #01000000b ;use timer 1 in 1t mode anl auxr, #10111111b ;use t imer 1 in 12t mode ;---------------------------------------------------------------------------------------------------------------------- setb r1 ; start up timer 1 setb es setb ea ret ;----------------------------------------------------------------------------------------------------------------------- ;portal parameter: a= the byte to send send_one_byte: ;send one byte clr es clr ti ;clear serial port transmit interrupt flag mov sbuf, a wait_send_finish: jnb ti, wait_send_finish ;wait to finish send clr ti setb es ret ;------------------------------------------------------------------------------------------------------------------------- end 7.3 timer/counter 2 mode of operation timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter as selected by c/t2 in the special function register t2con. timer 2 has four operation modes: capture mode, auto-reload mode (up or down counting), baud-rate generator mode and programable clock-out mode, which are selected by bits t2con and t2mod as shown in following table. timer 2 operating modes table rclk+tclk cp/rl2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 buad rate generator x x 0 (off) capture mode in the capture mode there are two options selected by bit exen2 in t2con. if exen2=0, timer 2 is a 16-bit timer or counter which upon overflowing sets bit tf2 (timer 2 overflow flag). this bit can then be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2=1, timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, th2 and tl2, to be captured into registers rcap2h and rcap2l, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and the exf2 bit, like tf2, can generate an interrupt which vectors to the same location as timer 2 overflow interrupt. tf2 and exf2 is ored to request the interrupt service. the capture mode is illustrated in following figure. 100
timer 2 interrupt sysclk tf2 control c/t2=0 c/t2=1 t2 pin t2ex pin mcu in 12t mode mcu in 6t mode tl2 (8 bits) rcap2l timer 2 in capture mode 12 6 tr2 th2 (8 bits) rcap2h exf2 transition detector control exen2 capture auto-reload mode in 16-bit auto-reload mode, timer 2 can be configured to count up or down. the counting direction is determined by dcen in special function register t2mod and t2ex pin. if dcen=0, counting up. if dcen=1, the counting direction is determined by t2ex pin. if t2ex=1, counting up, otherwise counting down. the following figure shows dcen=0, which enables timer 2 to count up automatically. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by firmware. if exen2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. timer 2 interrupt sysclk tf2 control c/t2=0 c/t2=1 t2 pin t2ex pin mcu in 12t mode mcu in 6t mode tl2 (8 bits) rcap2l timer 2 in auto-reload mode (dcen=0) 12 6 tr2 th2 (8 bits) rcap2h exf2 transition detector control exen2 reload 101
the following figure shows dcen=1, which enables timer 2 to count up or down. this mode allows pin t2ex to control the counting direction. when a logic 1 is applied at pin t2ex, timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt if the interrupt is enabled. this overflow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. a logic 0 applied to pin t2ex causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. this underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode. timer 2 interrupt sysclk tf2 control c/t2=0 c/t2=1 t2 pin t2ex pin mcu in 12t mode mcu in 6t mode tl2 (8 bits) rcap2l timer 2 in auto-reload mode (dcen=1) 12 6 tr2 th2 (8 bits) rcap2h exf2 ffh ffh toggle count direction 1=up 0=down overflow down counting reload value up counting reload value buad-rate generator mode timer2 can be configured to generate various baud-rate. bit tclk and/or rclk in t2con allow the serial port transmit and receive baud rates to be derived from either timer1 or timer2. when tclk=0, timer1 is used as the serial port transmit baud rate generator. when tclk=1, timer2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port baud rate. with these two bits, the serial port can have dif- ferent receive and transmit baud rates ? one generated from timer 1 and the other from timer 2. in brg mode, timers is operated very like auto-reload up-only mode except that the t2ex pin cannot control re- load. an overflow on timer 2 will load rcap2h, rcap2l contents onto timer2, but tf2 will not be set. a 1-to-0 transition on p2ex pin can set exf2 to request interrupt service if exen2=1. the following figure shows the timer 2 in baud rate generation mode to generate rx clock and tx clock into uart engine. the baud rate generation mode is like the auto-reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rate in uart mode 1 and mode 3 are determined by timer2?s overflow rate given below: baud rate= timer 2 overflow rate 16 (counting t2ex) the timer can be configured for either "timer" or "counter" operation. in the most typical applications, it is configured for "timer" operation( c/t2=0 )."timer" operation is a little different for timer 2 when it's being used as a baud rate generator. normally, as timer it would increment every machine clcye(thus at 1/6 or 1/12 the system clock).in that case the baud rate is given bu the formalu: baud rate= sysclk n[65536 - (rcap2h, rcap2l)] (as timer) when mcu in 12t mode, n=32; when mcu in 6t mode, n=16. 102
the timer 2 as a baud rate generator mode is valid only if rclk and/or tclk=1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable bit) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. it should be noted that when timer 2 is running (tr2=1) in "timer" function in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented at 1/2 the system clock or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. timer 2 interrupt sysclk 2 control c/t2=0 c/t2=1 t2 pin t2ex pin mcu in 12t mode mcu in 6t mode tl2 (8 bits) rcap2l timer 2 in baud-rate generator mode 12 6 tr2 th2 (8 bits) rcap2h exf2 transition detector control exen2 '0' '1' '1' '0' 16 16 '1' '0' timer 1 overflow smod rclk rx clock tx clock tclk reload the following program is an assembly language code that domestrates timer 2 of stc89xx series mcu acted as baud rate generator. ;/*------------------------------------------------------------------------------------------------------------*/ ;/* --- stc mcu international limited ----------------------------------------------------------------*/ ;/* --- stc 89xx series mcu timer 2 as baud rate generoter demo ------------------------*/ ;/* if you want to use the program or the program referenced in the */ ;/* article, please specify in which data and procedures from stc */ ;/*--------------------------------------------------------------------------------------------------------------*/ ;declare stc89xx series mcu sfrs ;sfrs associated with timer 2 and rs232 port t2con equ 0c8h tr2 equ t2con.2 ;tr2 is the second bit in sfr?t2con 103
rcap2l equ 0cah rcap2h equ 0cbh th2 equ 0cdh tl2 equ 0cch ;------------------------------------------------------------------------------------------------------------------ ;set baud rate auto-relaod value reload_count_high equ 0ffh ;reload_count_high must be set for 0ffh when the following parameters are used ;reload_count_low equ 0fah ;sysclk=22.1184mhz, baud=115200 ;reload_count_low equ 0eeh ;sysclk=22.1184mhz, baud=38400 ;reload_count_low equ 0f0h ;sysclk=20.000mhz, baud=38400 ;reload_count_low equ 0f6h ;sysclk=12.000mhz, baud=38400 ;reload_count_low equ 0fdh ;sysclk=11.059mhz, baud=115200 ;reload_count_low equ 0f7h ;sysclk=11.059mhz, baud=38400 ;reload_count_low equ 0f8h ;sysclk=10.000mhz, baud=38400 ;reload_count_low equ 0fbh ;sysclk=6.000mhz, baud=38400 ;reload_count_low equ 0fch ;sysclk=5.000mhz, baud=38400 ;reload_count_low equ 070h ;sysclk=11.059mhz, baud=2400 ;----------------------------------------------------------------------------------------------------- ;calculate auto-reload value ;------------------------------------------------------------------------------------------------------ ;reload=int(sysclk/baud/32+0.5), int means geting integer part and abandoning fractional part ;change the decimal reload to hexadecimal, and save the value from 1000h subtracting reload into rcap2h, rcap2l ;------------------------------------------------------------------------------------------------------ org 0000h ajmp main ;------------------------------------------------------------------------------------------------------ org 0023h ;rs232 serial port interrupt ajmp uart nop nop ;------------------------------------------------------------------------------------------------------- main: mov sp, #0e0h acall initial_uart ;initialize serial port mov r0, #30h ;send ten characters "0123456789" mov r2, #10 loop: mov a, r0 acall send_one_byte ;send one byte inc r0 djnz r2, loop wait1: sjmp wait1 ;dynamic stop 104
;--------------------------------------------------------------------------------------- uart: ;serial port interrupt service routine jbc ri, uart_1 reti ;inquire when transmitting uart_1: ;receive one byte push acc mov a, sbuf ;get the received byte acall send_one_byte ;send back the received byte pop acc reti ;------------------------------------------------------------------------------------- initial_uart: ;initialize serial port ;bit 7 6 5 4 3 2 1 0 ;scon sm0/fe sm1 sm2 ren tb8 rb8 ti ri mov scon, #50h ;0101,0000 8-bit variable baud rate, no parity init_rs232: mov a #reload_count_high ;baud auto-reload value mov rcap2h,a mov th2, a mov a, #reload_count_low mov rcap2l, a mov tl2, a mov t2con, #0x34 ;timer 2 as baud rate generator setb es ;enable serial port interrupt setb ea ret ;------------------------------------------------------------------------------------- ;send_one_byte: ;send one byte clr es clr ti ;clear uart transmit interrupt flag mov sbuf, a wait2: jnb ti, wait2 ;wait to finish transmitting clr ti setb es ret ;---------------------------------------------------------------------------------------- end ;---------------------------------------------------------------------------------------- 105
if timer 2 in programmabel clock out mode, some operations as shown below should be done: set t2oe bit in t2mod register. clear c/t2 bit in t2con register. determine the 16-bit reload value from the formula and enter it in the rcap2h and rcap2l registers. enter the same reload value as the initial value in the th2 and tl2 registers. set tr2 bit in t2con register to start the timer 2. ? ? ? ? ? timer 2 interrupt t2ex pin (p1.1) exf2 transition detector control exen2 sysclk control t2 pin (p1.0) mcu in 12t mode mcu in 6t mode tl2 (8 bits) rcap2l 12 6 tr2 th2 (8 bits) rcap2h c/t2 2 t2oe timer 2 in programmable clock output mode programmable clock output mode the stc89xx seires is able to generate a programmable clock output on p1.0. when t2oe bit is set and c//t2 bit is cleared, timer 2 overflow pulse will generate a 50% duty clock and output that to p1.0. the frequency of clock-out is calculated according to the following formula. baud rate= sysclk n[65536 - (rcap2h, rcap2l) when mcu in 12t mode, n=4; when mcu in 6t mode, n=2. note timer 2 overflag, tf2 will always not be set in this mode. the input clock, sysclk/2, increments the 16-bit timer (th2, tl2). the timer repeatedly counts to overflow from a loaded value. once overflows occur, the contents of (rcap2h, rcap2l) are loaded into (th2, tl2) for the consecutive counting. in the clock-out mode, timer2 rollovers will not generate an interrupt. this is similar to when timer 2 is used as a baud-rate generator. it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. note, however, that the baud-rate and the clock-out frequency depend on the same overflow rate of timer 2.the following figure shows the timer 2 in programmable clock output mode. 106
the following program is an assembly language code that domestrates timer 2 programable clock/pulse out function on p1.0. ;/*------------------------------------------------------------------------------------------------------------*/ ;/* --- stc mcu international limited ----------------------------------------------------------------*/ ;/* --- stc 89xx series mcu timer 2 in programmable clock/pulse output mode,on p1.0------------*/ ;/* if you want to use the program or the program referenced in the */ ;/* article, please specify in which data and procedures from stc */ ;/*--------------------------------------------------------------------------------------------------------------*/ ;declare stc89xx series mcu sfrs ;sfrs associated with timer 2 and rs232 port t2con equ 0c8h t2mod equ 0c9h tr2 equ t2con.2 ;tr2 is the second bit in sfr?t2con rcap2l equ 0cah rcap2h equ 0cbh th2 equ 0cdh tl2 equ 0cch ;timer/counter 2 control register t2con ; b7 b6 b5 b4 b3 b2 b1 b0 reset value ;bit-address cf ce cd cc cb ca c9 c8 ;t2con(c8h) tf2 exf2 rclk tclk exen2 tr2 c//t2 cp//rl2 00 ;t2mod register ; b7 b6 b5 b4 b3 b2 b1 b0 reset value ;t2con(c9h) - - - - - - t2oe dcen xxxxxx00b ;--------------------------------------------------------------------------------------------------------------- org 0000h ajmp main ;--------------------------------------------------------------------------------------------------------------- org 0100h main: mov sp, #0e0h mov p1, #0ffh ;turn off p1 port led acall set_t2_out_mode ;set timer 2 as high-speed pulse output mode mov dptr, #0fff0h ;set timer pulse output velocity acall set_t2_out_speed wait1: sjmp wait1 acall delay acall pause ;pause in order to observation mov dptr, #0ffe0h ;set timer pulse output velocity,lower 1/2 than last acall set_t2_out_speed acall delay acall pause ;pause in order to observation mov dptr #0ffd0h ;set timer pulse output velocity,lower 1/3 than last 107
acall set_t2_out_speed acall delay acall pause ;pause in order to observation wait2: sjmp wait2 ;dynamic stop ;------------------------------------------------------------------------------- delay: mov r1, #0 mov r2, #0 mov r3, #30 delay_loop: djnz r1, delay_loop djnz r2, delay_loop djnz r3, delaly_loop ret ;------------------------------------------------------------------------------- set_t2_out_mode: ;set timer2 as pulse output mode mov t2con, #0 ;set timer 2 as "timer" mode mov t2mod, #02 ;0000,0010, enable ;timer 2 overflow pulse outputting on p1.0 ;------------------------------------------------------------------------------- set_t2_out_speed: ;set timer 2 pulse output velocity clr tr2 ;disable timer 2 mov rcap2h, dph mov rcap2l, dpl setb tr2 ;triggle timer 2 ret ;------------------------------------------------------------------------------- pause: ;close timer 2 function clr tr2 mov p1, #0ffh ;turn off p1 port led acall delay ret ;------------------------------------------------------------------------------- end ;------------------------------------------------------------------------------- 108
chapter 8 uart with enhanced function the serial port of stc89xx series is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the reeeive register. (however,if the first byte still hasn?t been read by the time reception of the second byte is complete, one of the bytes will be lost). the serial port receive and transmit share the same sfr ? sbuf, but actually there is two sbuf registers in the chip, one is for transmit and the other is for receive. the serial port can be operated in 4 different modes: mode 0 provides synchronous communication while modes 1, 2, and 3 provide asynchronous communication. the asynchronous communication operates as a full-duplex universal asynchronous receiver and transmitter (uart), which can transmit and receive simultaneously and at different baud rates. serial communiction involves the transimission of bits of data through only one communication line. the data are transimitted bit by bit in either synchronous or asynchronous format. synchronous serial communication transmits ont whole block of characters in syschronization with a reference clock while asynchronous serial communication randomly transmits one character at any time, independent of any clock. symbol description address bit address and symbol msb lsb value after power-on or reset scon serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 0000 0000b sbuf serial buffer 99h xxxx xxxxb pcon power control 87h smod smod0 - pof gf1 gf0 pd idl 00x1 0000b ie interrupt enable a8h ea - et2 es et1 ex1 et0 ex0 0000 0000b ip interrupt priority low b8h - - pt2 ps pt1 px1 pt0 px0 xx00 0000b iph interrupt priority high b7h px3h px2h pt2h psh pt1h px1h pt0h px0h 0000 0000b saden slave address mask b9h 0000 0000b saddr slave address a9h 0000 0000b 109
scon register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name sm0/fe sm1 sm2 ren tb8 rb8 ti ri fe: framing error bit. the smod0 bit must be set to enable access to the fe bit 0: the fe bit is not cleared by valid frames but should be cleared by software. 1: this bit set by the receiver when an invalid stop bit id detected. sm0,sm1 : serial port mode bit 0/1. sm0 sm1 description baud rate 0 0 8-bit shift register sysclk/12 0 1 8-bit uart variable 1 0 9-bit uart sysclk/64 or sysclk/32(smod=1) 1 1 9-bit uart variable sm2 : enable the automatic address recognition feature in mode 2 and 3. if sm2=1, ri will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast address. in mode1, if sm2=1 then ri will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren : when set enables serial reception. tb8 : the 9th data bit which will be transmitted in mode 2 and 3. rb8 : in mode 2 and 3, the received 9th data bit will go into this bit. ti : transmit interrupt flag. ri : receive interrupt flag. sbuf register lsb bit 7654321 0 name it is used as the buffer register in transmission and reception. the serial port buffer register (sbuf) is really two buffers. writing to sbuf loads data to be transmitted, and reading sbuf accesses received data. these are two separate and distinct registers, the transimit write-only register, and the receive read-only register. pcon: power control register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name smod smod0 - pof gf1 gf0 pd idl smod: double baud rate control bit. 0 : disable double baud rate of the uart. 1 : enable double baud rate of the uart in mode 1,2,or 3. smod0: frame error select. 0 : scon.7 is sm0 function. 1 : scon.7 is fe function. note that fe will be set after a frame error regardless of the state of smod0. 110
ie: interrupt enable rsgister ea - et2 es et1 ex1 et0 ex0 (msb) (lsb) enable bit = 1 enables the interrupt . enable bit = 0 disables it . symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt will be acknowledged.if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. es ie.4 serial port interrupt enable bit ip: interrupt priority low register - - pt2 ps pt1 px1 pt0 px0 (msb) (lsb) priority bit = 1 assigns high priority . priority bit = 0 assigns low priority. symbol position function ps ip.4 serial port interrupt priority bit. iph: interrupt priority high register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name px3h px2h pt2h psh pt1h px1h pt0h px0h psh : if set, set priority for serial port highest saden: slave address mask register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name saddr: slave address register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name saddr register is combined with saden register to form given/broadcast address for automatic address recognition. in fact, saden function as the "mask" register for saddr register. the following is the example for it. saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 the given slave address will be checked except bit 1 is treated as "don't care". the broadcast address for each slave is created by taking the logical or of saddr and saden. zero in this result is considered as "don't care" and a broad cast address of all " don't care". this disables the automatic address detection feature. 111
8-bit shift register (mode 0) mode 0, selected by writing 0s into bits sm1 and sm0 of scon, puts the serial port into 8-bit shift register mode. serial data enters and exits through rxd, and txd outputs the shift clock. eight data bits are transmitted/ received with the least-significant (lsb) first. the baud rate is fixed at 1/12 the system clock cycle. the terms "rxd" and "txd" are misleading in this mode. the rxd line is used for both data input and output, and the txd line serves as the clock. transmission is initiated by any instruction that uses sbuf as a destination register. the ?write to sbuf? signal also loads a ?1? into the 9 th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full system clock cycle will elapse between "write to sbuf," and activation of send. send transfers the output of the shift register to the alternate output function line of p3.0, and also transfers shift clock to the alternate output function line of p3.1. at the falling edge of the shift clock, the contents of the shift register are shifted one position to the right. as data bits shift out to the right, ?0? come in from the left. when the msb of the data byte is at the output position of the shift register, then the ?1? that was initially loaded into the 9 th position is just to the left of the msb, and all positions to the left of that contains zeroes. this condition flags the tx control block to do one last shift and then deactivate send and set ti. both of these actions occur after "write to sbuf". reception is initiated by the condition ren=1 and ri=0. after that, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enables shift clock to the alternate output function line of p3.1.at receive is active, the contents of the receive shift register are shifted to the left one position. the value that comes in from the right is the value that was sampled at the p3.0 pin the rising edge of shift clock. as data bits come in from the right, ?1?s shift out to the left. when the ?0? that was initially loaded into the right- most position arrives at the left-most position in the shift register, it flags the rx control block to do one last shift and load sbuf. then receive is cleared and ri is set. 8.1 uart mode of operation 112
stc mcu internal bus sbuf zero detector tx control shift send start tx clock ti d s q cl rx control shift receive start rx clock ri input shift reg sbuf stc mcu internal bus write to sbuf shift rxd/p3.0 output function 11111110 shift clock txd/p3.1 output function shift rxd/p3.0 input function load sbuf read sbuf serial port interrupt ren ri write to sbuf send shift d1 d0 d2 d3 d4 d5 d6 d7 rxd(data out) txd(shift clock) ti write to scon(clear ri) ri receive shift txd(shift clock) rxd(data in) d0 d1 d2 d3 d4 d5 d6 d7 transmit receive serial port mode 0 sysclk/12 113
8-bit uart with variable baud rate (mode 1) in mode 1 the stc89xx serial port operates as an 8-bit uart with variable baud rate. a uart, or "universal asynchronous receiver/transmitter," is a device that receives and transmits serial data with each data character preceded by a start bit(low) and followed by a stop bit(high). a parity bit is sometimes inserted between the last data bit and the stop bit. the essential operation of a uart is parallel-to-serial conversion of output data and serial-to-parallel conversion of input data. in mode 1, 10 bits are transmitted through txd or received through rxd. the frame data includes a start bit (always 0), 8 data bits (lsb first) and a stop bit (always 1). for a receive operation, the stop bit goes into rb8 in sfr ? scon. the baud rate is determined by the overflow rate of timer 1 or timer 2 . baud rate in mode 1 = (2 smod /32 ) x timer 1 overflow rate or = (2 smod /16 ) x timer 2 overflow rate transmission is initiated by any instruction that uses sbuf as a destination register. the ?write to sbuf? signal also loads a ?1? into the 9 th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually happens at the next rollover of divided-by-16 counter. thus the bit times are synchronized to the divided-by-16 counter, not to the ?write to sbuf? signal. the transmission begins with activation of send , which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeroes are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9 th position is just to the left of the msb, and all positions to the left of that contain zeroes. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10 th divide-by-16 rollover after ?write to sbuf.? reception is initiated by a 1-to-0 transition detected at rxd. for this purpose, rxd is sampled at a rate of 16 times the established baud rate. when a transition is detected, the divided-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divided-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7 th , 8 th and 9 th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done to reject noise. in order to reject false bits, if the value accepted during the first bit time is not a 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit is valid, it is shifted into the input shift register, and reception of the res t of the frame proceeds. as data bits come in from the right, ?1?s shift out to the left. when the start bit arrives at the left most position in the shift register,(which is a 9-bit register in mode 1), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8 and to set ri is generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1) ri=0 and 2) either sm2=0, or sm2=0 and the received stop bit = 1 if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition in rxd. 114
serial port mode 1 stc mcu internal bus sbuf zero detector tx control shift start tx clock ti d s q cl rx control shift load sbuf start rx clock ri input shift reg (9 bits) sbuf stc mcu internal bus write to sbuf 1ffh 16 shift load sbuf read sbuf serial port interrupt send data tb8 txd 16 1-to-0 transition detector sample bit detector rxd rclk tclk "0" "1" 2 smod =0 smod =1 "0" "1" timer 2 overflow timer 1 overflow write to sbuf send shift data d1 d0 txd d2 d3 d4 d5 d6 d7 start bit stop bit ti transmit tx clock d1 d0 rxd d2 d3 d4 d5 d6 d7 start bit stop bit rx clock 16 reset shift bit detector sample times ri receive 115
9-bit uart with fixed baud rate (mode 2) when sm1=1 and sm0=0, the serial port operates in mode 2 as a 9-bit uart with a fixed baud rate. 11 bits are transmitted through txd or received through rxd. the frame data includes a start bit(0), 8 data bits, a programmable 9th data bit and a stop bit(1). on transmit, the 9th data bit comes from tb8 in scon. on receive, the 9th data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 the system clock cycle. baud rate in mode 2 = (2 smod /64) x sysclk transmission is initiated by any instruction that uses sbuf as a destination register. the ?write to sbuf? signal also loads tb8 into the 9 th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually happens at the next rollover of divided-by-16 counter. thus the bit times are synchronized to the divided-by-16 counter, not to the ?write to sbuf? signal. the transmission begins when /send is activated, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a ?1?(the stop bit) into the 9 th bit position on the shift register. thereafter, only ?0?s are clocked in. as data bits shift out to the right, ?0?s are clocked in from the left. when tb8 of the data byte is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contains ?0?s. this condition flags the tx control unit to do one last shift, then deactivate /send and set ti. this occurs at the 11 th divided-by-16 rollover after ?write to sbuf?. reception is initiated by a 1-to-0 transition detected at rxd. for this purpose, rxd is sampled at a rate of 16 times whatever baud rate has been estabished. when a transition is detected, the divided-by-16 counter is immediately reset, and 1ffh is written into the input shift register. at the 7 th , 8 th and 9 th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done to reject noise. in order to reject false bits, if the value accepted during the first bit time is not a 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. if the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. as data bits come in from the right, ?1?s shift out to the left. when the start bit arrives at the leftmost position in the shift register,(which is a 9-bit register in mode-2 and 3), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8 and to set ri is generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1) ri=0 and 2) either sm2=0, or the received 9 th data bit = 1 if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the first 8 data bits go into sbuf, and ri is activated. at this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition at the rxd input. note that the value of received stop bit is irrelevant to sbuf, rb8 or ri. 116
stc mcu internal bus sbuf zero detector tx control shift start tx clock ti d s q cl rx control shift load sbuf start rx clock ri input shift reg (9 bits) sbuf stc mcu internal bus write to sbuf 1ffh 16 shift load sbuf read sbuf serial port interrupt send data tb8 txd 16 1-to-0 transition detector sample bit detector rxd stop bit gen. 2 smod=0 smod=1 mode 2 (smod is pcon.7) sysclk/2 write to sbuf send shift data d1 d0 txd d2 d3 d4 d5 d6 d7 start bit stop bit ti transmit tx clock d1 d0 rxd d2 d3 d4 d5 d6 d7 start bit stop bit rx clock bit detector sample times receive stop bit gen tb8 rb8 shift ri serial port mode 2 117
9-bit uart with variable baud rate (mode 3) mode 3, 9-bit uart with variable baud rate, is the same as mode 2 except the baud rate is variable. baud rate in mode 3 = (2 smod /32 ) x timer 1overflow rate or = (2 smod /16 ) x timer 2 overflow rate in all four modes, transmission is initiated by any instruction that use sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit with 1-to-0 transition if ren=1. 8.2 frame error detection when used for frame error detect, the uart looks for missing stop bits in the communication. a missing bit in stop bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6(smod0). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe, scon.7 can only be cleared by software.refer to the following figure. 8.3 multiprocessor communications modes 2 and 3 have a special provision for multiproceasor communications. in these modes 9 data bits are re- ceived.the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received,the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows. when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave.an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however,will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed.the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren?t be- ing addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0,and in mode 1 can be used to check the validity of the stop bit. in a mode 1 recep- tion, if sm2 = 1, the receive interrupt will not be activated unless a vatid stop bit is received. d1 d0 d2 d3 d4 d5 d6 d7 start bit stop bit d8 sm0/fe sm1 sm2 ren tb8 rb8 ti ri 9-bit data set fe bit if stop=0 sm0 to uart mode control pcon.6/smod0 scon uart frame error detection 1 0 118
serial port mode 3 stc mcu internal bus sbuf zero detector tx control shift start tx clock ti d s q cl rx control shift load sbuf start rx clock ri input shift reg (9 bits) sbuf stc mcu internal bus write to sbuf 1ffh 16 shift load sbuf read sbuf serial port interrupt send data tb8 txd 16 1-to-0 transition detector sample bit detector rxd rclk tclk "0" "1" 2 smod =0 smod =1 "0" "1" timer 2 overflow timer 1 overflow write to sbuf send shift data d1 d0 txd d2 d3 d4 d5 d6 d7 start bit stop bit ti transmit tx clock d1 d0 rxd d2 d3 d4 d5 d6 d7 start bit stop bit rx clock 16 reset bit detector sample times receive stop bit gen tb8 rb8 shift ri 119
8.4 automatic address recognition automatic address recognition is a future which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9-bit uart modes, mode 2 and mode 3, the receive interrupt flag(ri) will be automatically set when the received byte contains either the ?given? address or the ?broadcast? address. the 9-bit mode requires that the 9 th information bit is a ?1? to indicate that the received information is an address and not data. the 8-bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave?s address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are ?don?t care?. the saden mask can be logically anded with the saddr to create the ?given? address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized which excluding others. the following examples will help to show the versatility of this scheme : slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the previous example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a ?0? in bit 0 and it ignores bit 1. slave 1 requires a ?0? in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 11000010 since slave 1 requires a ?0? in bit 1. a unique address for slave 1 would be 11000001 since a ?1? in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0=0 (for slave 0) and bit 1 =0 (for salve 1). thus, both could be addressed with 11000000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx 120
in the above example the differentiation among the 3 slaves is in the lower 3 address bits.slave 0 requires that bit0 = 0 and it can be uniquely addressed by 11100110. slave 1 requires that bit 1=0 and it can be uniquely addressed by 11100101. slave 2 requires that bit 2=0 and its unique address is 11100011. to select salve 0 and 1 and exclude slave 2, use address 11100100, since it is necessary to make bit2=1 to exclude slave 2. the broadcast address for each slave is created by taking the logic or of saddr and saden. zeros in this result are trended as don?t cares. in most cares, interpreting the don?t cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with ?0?s. this produces a given address of all ?don?t cares as well as a broadcast address of all ?don?t cares?. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51-type uart drivers which do not make use of this feature. example: write an program that continually transmits characters from a transmit buffer. if incoming characters are detected on the serial port, store them in the receive buffer starting at internal ram location 50h. assume that the stc89xx mcu serial port has already been initialized in mode 1. solution: org 0030h mov r0, #30h ;pointer for tx buffer mov r1, #50h ;pointer for rx buffer loop: jb ri, receive ;character received? ;yes: process it jb ti, tx ;previous character transmitted ? ;yes: process it sjmp loop ;no: continue checking tx: mov a, @r0 ;get character from tx buffer mov c, p ;put parity bit in c clr c ;change to odd parity mov acc.7, c ;add to character code clr ti ;clear transmit flag mov sbuf, a ;send character clr acc.7 ;strip off parity bit inc r0 ;point to next character in buffer cjne r0, #50h, loop ;end of buffer? ;no: continue mov r0, #30h ;yes: recycle sjmp loop ;continue checking rx: clr ri ;clear receive flag mov a, sbuf ;read character into a mov c, p ;for odd parity in a, p should be set cpl c ;complementing correctly indicates "error" clr acc.7 ;strip off parity mov @r1, a ;store received character in buffer inc r1 ;point to next location in buffer sjmp loop ;continue checking end 121
8.5 buad rates the baud rate in mode 0 is fixed: sysclk 12 mode 0 baud rate = the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod =0 (which is the value on reset), the baud rate 1 / 64 the system clock cycle. if smod = 1, the baud rate is 1 / 32 the system clock cycle . 2 smod 64 mode 2 baud rate = (sysclk) (sysclk) in the stc89xx series, the baud rates in modes 1 and 3 are determined by timer1 or timer 2 overflow rate. the baud rate in mode 1 and 3 are fixed: mode 1,3 baud rate = (2 smod /32 ) x timer 1 overflow rate = (2 smod /32 ) x timer 2 overflow rate timer 1 overflow rate = (sysclk/12)/(256 - th1); timer 2 overflow rate = sysclk/(65536-(rcap2h,rcap2l)) when timer 1 is used as the baud rate generator, the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either ?timer? or ?cormter? operation, and in any of its 3 running modes. in the most typcial applications, it is configured for ?timer? operation, in the auto-reload mode (high nibble of tmod = 0010b). one can achieve very low baud rate with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a l6-bit software reload. the following table lists various commonly used baud rates and how they can be obtained from timer 1. baud rate f osc smod timer 1 c/t mode reload value mode 0 max: 1mhz mode 2 max: 375k mode 1,3: 62.5k 19.2k 9.6k 4.8k 2.4k 1.2k 137.5 110 110 12mhz 12mhz 12mhz 11.059mhz 11.059mhz 11.059mhz 11.059mhz 11.059mhz 11.986mhz 6mhz 12mhz x 1 1 1 0 0 0 0 0 0 0 x x 0 0 0 0 0 0 0 0 0 x x 2 2 2 2 2 2 2 2 1 x x ffh fdh fdh fah f4h e8h 1dh 72h feebh timer 1 generated commonly used baud rates when timer 2 is used as the baud rate generator (either tclk or rclk in t2con is '1'), the baud rate is as follows, mode 1,3 baud rate = 2 smod sysclk sysclk 32(65536-(rcap2h,rcap2l)) 65536-(rcap2h,rcap2l)) 122
the following table lists various commonly used baud rates generated by timer 2. baud rate system clocks /mhz timer 2 12t mode 6t mode rcap2h rcap2l 375 000 750 000 12 ff ff 9 600 19 200 12 ff d9 2 800 9 600 12 ff b2 2 400 4 800 12 ff 64 1 200 2 400 12 fe c8 300 600 12 fb 1e 110 220 12 f2 af 300 600 6 fd 8f 110 220 6 f9 57 123
chapter 9 iap / eeprom the isp in stc89xx series makes it possible to update the user?s application program and non-volatile application data (in iap-memory) without removing the mcu chip from the actual end product. this useful capability makes a wide range of field-update applications possible. (note isp needs the loader program pre-programmed in the isp-memory.) in general, the user needn?t know how isp operates because stc has provided the standard isp tool and embedded isp code in stc shipped samples. but, to develop a good program for isp function, the user has to understand the architecture of the embedded flash. the embedded flash consists of 90(max) pages. each page contains 512 bytes. dealing with flash, the user must erase it in page unit before writting (programming) data into it. erasing flash means setting the content of that flash as ffh. two erase modes are available in this chip. one is mass mode and the other is page mode. the mass mode gets more performance, but it erases the entire flash. the page mode is something performance less, but it is flexible since it erases flash in page unit. unlike ram?s real-time operation, to erase flash or to write (program) flash often takes long time so to wait finish. furthermore,it is a quite complex timing procedure to erase/program flash. fortunately, the stc89xx carried with convenient mechanism to help the user read/change the flash content. just filling the target address and data into several sfr, and triggering the built-in isp automation, the user can easily erase, read, and program the embedded flash and option registers. the in-application program feature is designed for user to read/write nonvolatile data flash. it may bring great help to store parameters those should be independent of power-up and power-done action. in other words, the user can store data in data flash memory, and after he shutting down the mcu and rebooting the mcu, he can get the original value, which he had stored in. the user can program the data flash according to the same way as isp program, so he should get deeper un- derstanding related to sfr isp_data, isp_addrl, isp_addrh, isp_cmd, isp_trig, and isp_contr. 9.1 iap / isp control register the following special function registers are related to the iap/isp operation. all these registers can be accessed by software in the user?s application program. symbol description address bit address and symbol msb lsb value after power-on or reset isp_data isp/iap flash data register e2h 1111 1111b isp_addrh isp/iap flash address high e3h 0000 0000b isp_addrl isp/iap flash address low e4h 0000 0000b isp_cmd isp/iap flash command register e5h -----ms2ms1ms0 xxxx x000b isp_trig isp/iap flash command trigger e6h xxxx xxxxb isp_contr isp/iap control register e7h ispen swbs swrst -- wt2 wt1 wt0 000x x000b pcon power control 87h smod smod0 - pof gf1 gf0 pd idl 00x1 0000b 124
isp_addrl: isp/iap flash address low lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name isp_addrl is the low port for all isp/iap modes. in page erase operation, it is ignored. isp_cmd: isp/iap flash command register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name - - - - - ms2 ms1 ms0 b7~b2: reserved. ms2, ms1, ms0 : isp/iap operating mode selection. iap_cmd is used to select the flash mode for performing numerous isp/iap function or used to access protected sfrs. 0, 0, 0 : standby 0, 0, 1 : data flash/eeprom read. 0, 1, 0 : data flash/eeprom program. 0, 1, 1 : data flash/eeprom page erase. isp_trig: isp/iap flash command trigger. lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name isp_trig is the command port for triggering isp/iap activity and protected sfrs access. if isp_trig is filled with sequential 0x46h, 0xb9h and if ispen(isp_contr.7) = 1, isp/iap activity or protected sfrs access will triggered. isp_data: isp/iap flash data register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name isp_data is the data port register for isp/iap operation. the data in isp_data will be written into the desired address in operating isp/iap write and it is the data window of readout in operating isp/ iap read. isp_addrh: isp/iap flash address high lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name isp_addrh is the high-byte address port for all isp/iap modes. isp_addrh[7:5] must be cleared to 000, if one bit of isp_addrh[7:5] is set, the iap/isp write function must fail. 125
isp_contr: isp/iap control register lsb bit b7 b6 b5 b4 b3 b2 b1 b0 name ispen swbs swrst - - wt2 wt1 wt0 ispen : isp/iap operation enable. 0 : global disable all isp/iap program/erase/read function. 1 : enable isp/iap program/erase/read function. swbs: software boot selection control. 0 : boot from main-memory after reset. 1 : boot from isp memory after reset. swrst: software reset trigger control. 0 : no operation 1 : generate software system reset. it will be cleared by hardware automatically. note: software reset actions could reset other sfr, but it never influence bits ispen and swbs. the ispen and swbs only will reset by power-up action, while not software reset. b3: reserved. software must write ?0? on this bit when isp_contr is written. wt2~wt0 : waiting time selection while flash is busy. setting wait times cpu wait times wt2 wt1 wt0 read program <=55us sector erase <=21ms recommended system clock frequency (mhz) 0 1 1 6 sysclks 30 sysclks 5471 sysclks 5mhz 0 1 0 11 sysclks 60 sysclks 10942 sysclks 10mhz 0 0 1 22 sysclks 120sysclks 21885sysclks 20mhz 0 0 0 43 sysclks 240 sysclks 43769 sysclks 40mhz 9.2 stc89xx series internal eeprom selection table stc89xx series mcu internal eeprom selection table type eeprom (byte) sector numbers begin_sector begin_address end_sector end_address stc89c/le51rc 4k 8 0000h 0fffh stc89c/le52rc 4k 8 0000h 0fffh stc89c/le54rd+ 45k 90 0000h 0b3ffh stc89c/le58rd+ 29k 58 0000h 73ffh 126
9.3 iap/eeprom assembly language program introduction ; /*it is decided by the assembler/compiler used by users that whether the sfrs addresses are declared by the data or the equ directive*/ isp_data data 0e2h or isp_data equ 0e2h isp_addrh data 0e3h or isp_addrh equ 0e3h isp_addrl data 0e4h or isp_addrl equ 0e4h isp_cmd data 0e5h or isp_cmd equ 0e5h isp_trig data 0e6h or isp_trig equ 0e6h isp_contr data 0e7h or isp_contr equ 0e7h ;/*define isp/iap/eeprom command and wait time*/ isp_iap_byte_read equ 1 ;byte-read isp_iap_byte_program equ 2 ;byte-program isp_iap_sector_erase equ 3 ;sector-erase wait_time equ 0 ;set wait time ;/*byte-read*/ mov isp_addrh, #byte_addr_high ;set isp/iap/eeprom address high mov isp_addrl, #byte_addr_low ;set isp/iap/eeprom address low mov isp_contr, #wait_time ;set wait time orl isp_contr, #10000000b ;open isp/iap function mov isp_cmd, #isp_iap_byte_read ;set isp/iap byte-read command mov isp_trig, #46h ;send trigger command1 (0x46) mov isp_trig, #0b9h ;send trigger command2 (0xb9) nop ;cpu will hold here until isp/iap/eeprom operation complete mov a, isp_data ;read isp/iap/eeprom data ;/*disable isp/iap/eeprom function, make mcu in a safe state*/ mov isp_contr, #00000000b ;close isp/iap/eeprom function mov isp_cmd, #00000000b ;clear isp/iap/eeprom command ;mov isp_trig, #00000000b ;clear trigger register to prevent mistrigger ;mov isp_addrh, #0 ;set address high(00h), data ptr point to non-eeprom area ;mov isp_addrl, #0 ;clear iap address to prevent misuse setb ea ;set global enable bit ;/*byte-program, if the byte is null(0ffh), it can be programmed; else, mcu must operate sector-erase firstly, and then can operate byte-program.*/ mov isp_data, #one_data ;write isp/iap/eeprom data mov isp_addrh, #byte_addr_high ;set isp/iap/eeprom address high mov isp_addrl, #byte_addr_low ;set isp/iap/eeprom address low mov isp_contr, #wait_time ;set wait time orl isp_contr, #10000000b ;open isp/iap function mov isp_cmd, #isp_iap_byte_read ;set isp/iap byte-read command mov isp_trig, #46h ;send trigger command1 (0x46) mov isp_trig, #0b9h ;send trigger command2 (0xb9) nop ;cpu will hold here until isp/iap/eeprom operation complete 127
;/*disable isp/iap/eeprom function, make mcu in a safe state*/ mov isp_contr, #00000000b ;close isp/iap/eeprom function mov isp_cmd, #00000000b ;clear isp/iap/eeprom command ;mov isp_trig, #00000000b ;clear trigger register to prevent mistrigger ;mov isp_addrh, #0 ;set address high(00h), data ptr point to non-eeprom area ;mov isp_addrl, #0 ;clear iap address to prevent misuse setb ea ;set global enable bit ;/*erase one sector area, there is only sector-erase instead of byte-erase, every sector area account for 512 bytes*/ mov isp_addrh, #sectot_first_byte_addr_high ;set the sector area starting address high mov isp_addrl, #sectot_first_byte_addr_low ;set the sector area starting address low mov isp_contr, #wait_time ;set wait time orl isp_contr, #10000000b ;open isp/iap function mov isp_cmd, #isp_iap_sector_erase ;set sectot-erase command mov isp_trig, #46h ;send trigger command1 (0x46) mov isp_trig, #0b9h ;send trigger command2 (0xb9) nop ;cpu will hold here until isp/iap/eeprom operation complete ;/*disable isp/iap/eeprom function, make mcu in a safe state*/ mov isp_contr, #00000000b ;close isp/iap/eeprom function mov isp_cmd, #00000000b ;clear isp/iap/eeprom command ;mov isp_trig, #00000000b ;clear trigger register to prevent mistrigger ;mov isp_addrh, #0 ;set address high(00h), data ptr point to non-eeprom area ;mov isp_addrl, #0 ;clear iap address to prevent misuse 128
9.4 operating internal eeprom demo by assembly language ;/*-------------------------------------------------------------------------------------*/ ;/* --- stc mcu international limited ----------------------------------------*/ ;/* --- stc89xx series mcu isp/iap/eeprom demo -----------------------*/ ;/* if you want to use the program or the program referenced in the */ ;/* article, please specify in which data and procedures from stc */ ;/*-------------------------------------------------------------------------------------*/ ;/*declare sfrs associated with the iap */ isp_data equ 0e2h ;flash data register isp_addrh equ 0e3h ;flash address high isp_addrl equ 0e4h ;flash address low isp_cmd equ 0e5h ;flash command register isp_trig equ 0e6h ;flash command trigger isp_contr equ 0e7h ;flash control register ;/*define isp/iap/eeprom operation const for iap_contr*/ enable_isp equ 80h ;if sysclk>20mhz ;enable_isp equ 81h ;if sysclk<20mhz enable_isp equ 82h ;if sysclk<10mhz ;enable_isp equ 83h ;if sysclk<5mhz debug_data equ 5ah ;select mcu type data_flash_start_address equ 2000h ;stc89c/le52rc ;------------------------------------------------- org 0000h ljmp main ;------------------------------------------------- org 0100h main: mov p1, #0f0h ;1111,0000 system reset ok lcall delay ;delay mov p1, #0f0h ;1111,0000 system reset ok lcall delay ;delay mov sp, #0e0h ;initialize stack pointer ;********************************** ;read the first byte written into flash main1: mov dptr, #data_flash_start_address lcall byte_read mov 40h, a cjne a, #debug_data, data_not_equ_debug_data 129
data_is_debug_data: mov p1, #0111111b ;(data_fl ash_start_address) = #5a, ;turn on p1.7 led lcall delay ;delay mov a, 40h cpl a mov p1, a ;data is right and showed in port 1 wait1: sjmp wait ;stop data_not_equ_debug_data: mov p1, #11110111b ;(data_flash_start_address) != #5a, ;turn on p1.3 led lcall delay ;delay mov a, 40h cpl a mov p1, a ;data is error and showed in port 1 lcall delay ;delay mov dptr, #data_flash_start_address acall sector_erase ;sector erase, ;(data_flash_start_address) != #debug_data mov dptr, #data_flash_start_address mov a, #debug_data ;write debug_data into falsh acall byte_program ;byte-program mov p1, #11011111b ;t urn on p1.3 led first, then turn on p1.5 led wait2: sjmp wait2 ;stop here after byte-program ;**************************************************** ;------------------------------------------------------------------------------ ;read one byte byte_read: mov isp_contr, #enable_isp ;enable iap/isp function ;determine flash wait time mov isp_cmd, #01 ;select read ap mode mov isp_addrh, dph ;fill page address in isp_addrh&isp_addrl mov isp_addrl, dpl clr ea mov isp_trig, #46h ;trigger isp processing mov isp_trig, #0b9h ;trigger isp processing nop mov a, isp_data ;get the data in isp_data setb ea ;now in processing.(cpu will halt here before completing) acall iap_disable ;disable iap function, ;clear some registers associated with isp ret 130
;------------------------------------------------------------------------ ;byte-program byte_program: mov isp_contr, #enable_isp ;enable iap function, ;determine flash wait time mov isp_cmd, #02h ;select byte program mode mov isp_addrh, dph ;fill page address in isp_addrh&isp_addrl mov isp_addrl, dpl mov isp_data, a ;save the value into isp_data clr ea mov isp_trig, #46h ;trigger isp processing mov isp_trig, #0b9h ;trigger isp processing nop setb ea acall iap_disable ;disable iap function, ;clear some registers associated with isp ret ;---------------------------------------------------------------------------- ;sector-erase sector_erase: mov isp_contr, #enable_isp ;enable iap function, ;determine flash wait time mov isp_cmd, #03h ;select page erase mode mov isp_addrh, dph ;fill page address in isp_addrh&isp_addrl mov isp_addrl, dpl clr ea mov isp_trig, #46h ;trigger isp processing mov isp_trig, #0b9h ;trigger isp processing nop setb ea acall iap_disable ;disable iap function, ;clear some registers associated with isp ret ;---------------------------------------------------------------------------- trigger_isp: clr ea mov isp_trig, #46h ;trigger isp processing mov isp_trig, #0b9h ;trigger isp processing nop setb ea ret ;---------------------------------------------------------------------------- iap_disable: ;disable iap function, cleal some registers associated with isp mov isp_contr, #0 mov isp_cmd, #0 mov isp_trig #0 ret 131
;---------------------------------------------------------- delay: clr a mov r0, a mov r1, a mov r2, #20 delay_loop: mov r0, delay_loop mov r1, delay_loop mov r2, delay_loop ret ;---------------------------------------------------------------- end ;******************************************* 132
appendix a: assembly language programming introduction assembly language is a computer language lying between the extremes of machine language and high-level language like pascal or c use words and statements that are easily understood by humans, although still a long way from "natural" language.machine language is the binary language of computers.a machine language program is a series of binary bytes representing instructions the computer can execute. assembly language replaces the binary codes of machine language with easy to remember "mnemonics"that facilitate programming.for example, an addition instruction in machine language might be represented by the code "10110011".it might be represented in assembly language by the mnemonic "add".programming with mnemonics is obviously preferable to programming with binary codes. of course, this is not the whole story. instructions operate on data, and the location of the data is specified by various "addressing modes" emmbeded in the binary code of the machine language instruction. so, there may be several variations of the add instruction, depending on what is added. the rules for specifying these variations are central to the theme of assembly language programming. an assembly language program is not executable by a computer. once written, the program must undergo translation to machine language. in the example above, the mnemonic "add" must be translated to the binary code "10110011". depending on the complexity of the programming environment, this translation may involve one or more steps before an executable machine language program results. as a minimum, a program called an "assembler" is required to translate the instruction mnemonics to machine language binary codes. afurther step may require a "linker" to combine portions of program from separate files and to set the address in memory at which th program may execute. we begin with a few definitions. an assembly language program i a program written using labels, mnemonics, and so on, in which each statement corresponds to a machine instruction. assembly language programs, often called source code or symbolic code, cannot be executed by a computer. a machine language program is a program containing binary codes that represent instructions to a computer. machine language programs, often called object code, are executable by a computer. a assembler is a program that translate an assembly language program into a machine language program. the machine language program (object code) may be in "absolute" form or in "relocatable" form. in the latter case, "linking" is required to set the absolute address for execution. a linker is a program that combines relocatable object programs (modules) and produces an absolute object program that is executable by a computer. a linker is sometimes called a "linker/locator" to reflect its separate functions of combining relocatable modules (linking) and setting the address for execution (locating). a segment is a unit of code or data memory. a segment may be relocatable or absolute. a relocatable segment has a name, type, and other attributes that allow the linker to combine it with other paritial segments, if required, and to correctly locate the segment. an absolute segment has no name and cannot be combined with other segments. a module contains one or more segments or partial segments. a module has a name assigned by the user. the module definitions determine the scope of local symbols. an object file contains one or more modules. a module may be thought of as a "file" in many instances. a program consists of a single absolute module, merging all absolute and relocatable segments from all input modules. a program contains only the binary codes for instructions (with address and data constants) that are understood by a computer. 133
assembler operation there are many assembler programs and other support programs available to facilitate the development of applications for the 8051 microcontroller. intel's original mcs-51 family assembler, asm51, is no longer available commercially. however, it set the standard to which the others are compared. asm51 is a powerful assembler with all the bells and whistles. it is available on intel development systems and on the ibm pc family of microcomputers. since these "host" computers contain a cpu chip other than the 8051, asm51 is called a cross assembler. an 8051 source program may be written on the host computer (using any text editor) and may be assembled to an object file and listing file (using asm51), but the program may not be executed. since the host system's cpu chip is not an 8051, it does not understand the binary instruction in the object file. execution on the host computer requires either hardware emulation or software simulation of the target cpu. a third possibility is to download the object program to an 8051-based target system for execution. asm51 is invoked from the system prompt by asm51 source_file [assembler_controls] the source file is assembled and any assembler controls specified take effect. the assembler receives a source file as input (e.g., program.src) and generates an object file (program.obj) and listing file (program. lst) as output. this is illustrated in figure 1. since most assemblers scan the source program twice in performing the translation to machine language, they are described as two-pass assemblers. the assembler uses a location counter as the address of instructions and the values for labels. the action of each pass is described below. program.src asm51 program.obj program.lst figure 1 assembling a source program legend utility program user file pass one during the first pass, the source file is scanned line-by-line and a symbol table is built. the location counter defaults to 0 or is set by the org (set origin) directive. as the file is scanned, the location counter is incremented by the length of each instruction. define data directives (dbs or dws) increment the location counter by the number of bytes defined. reserve memory directives (dss) increment the location counter by the number of bytes reserved. each time a label is found at the beginning of a line, it is placed in the symbol table along with the current value of the location counter. symbols that are defined using equate directives (equs) are placed in the symbol table along with the "equated" value. the symbol table is saved and then used during pass two. pass two during pass two, the object and listing files are created. mnemonics are converted to opcodes and placed in the output files. operands are evaluated and placed after the instruction opcodes. where symbols appear in the operand field, their values are retrieved from the symbol table (created during pass one) and used in calculating the correct data or addresses for the instructions. since two passes are performed, the source program may use "forward references", that is, use a symbol before it is defined. this would occur, for example, in branching ahead in a program. 134
the object file, if it is absolute, contains only the binary bytes (00h-0fh) of the machine language program. a relocatable object file will also contain a sysmbol table and other information required for linking and locating. the listing file contains ascii text codes (02h-7eh) for both the source program and the hexadecimal bytes in the machine language program. a good demonstration of the distinction between an object file and a listing file is to display each on the host computer's crt display (using, for example, the type command on ms-dos systems). the listing file clearly displays, with each line of output containing an address, opcode, and perhaps data, followed by the program statement from the source file. the listing file displays properly because it contains only ascii text codes. displaying the object file is a problem, however. the output will appear as "garbage", since the object file contains binary codes of an 8051 machine language program, rather than ascii text codes. assembly language program format assembly language programs contain the following: machine instructions assembler directives assembler controls comments ? ? ? ? machine instructions are the familiar mnemonics of executable instructions (e.g., anl). assembler directives are instructions to the assembler program that define program structure, symbols, data, constants, and so on (e.g., org). assembler controls set assembler modes and direct assembly flow (e.g., $title). comments enhance the readability of programs by explaining the purpose and operation of instruction sequences. those lines containing machine instructions or assembler directives must be written following specific rules understood by the assembler. each line is divided into "fields" separated by space or tab characters. the general format for each line is as follows: [label:] mnemonic [operand] [, operand] [?] [;commernt] only the mnemonic field is mandatory. many assemblers require the label field, if present, to begin on the left in column 1, and subsequent fields to be separated by space or tab charecters. with asm51, the label field needn't begin in column 1 and the mnemonic field needn't be on the same line as the label field. the operand field must, however, begin on the same line as the mnemonic field. the fields are described below. label field a label represents the address of the instruction (or data) that follows. when branching to this instruction, this label is usded in the operand field of the branch or jump instruction (e.g., sjmp skip). whereas the term "label" always represents an address, the term "symbol" is more general. labels are one type of symbol and are identified by the requirement that they must terminate with a colon(:). symbols are assigned values or attributes, using directives such as equ, segment, bit, data, etc. symbols may be addresses, data constants, names of segments, or other constructs conceived by the programmer. symbols do not terminate with a colon. in the example below, par is a symbol and start is a label (which is a type of symbol). par equ 500 ;"par" is a symbol which ;represents the value 500 start: mov a,#0ffh ;"start" is a label which ;represents the address of ;the mov instruction a symbol (or label) must begin with a letter, question mark, or underscore (_); must be followed by letters, digit, "?", or "_"; and can contain up to 31 characters. symbols may use upper- or lowercase characters, but they are treated the same. reserved words (mnemonics, operators, predefined symbols, and directives) may not be used. 135
mnemonic field intruction mnemonics or assembler directives go into mnemonic field, which follows the label field. examples of instruction mnemonics are add, mov, div, or inc. examples of assembler directives are org, equ, or db. operand field the operand field follows the mnemonic field. this field contains the address or data used by the instruction. a label may be used to represent the address of the data, or a symbol may be used to represent a data constant. the possibilities for the operand field are largely dependent on the operation. some operations have no operand (e.g., the ret instruction), while others allow for multiple operands separated by commas. indeed, the possibilties for the operand field are numberous, and we shall elaborate on these at length. but first, the comment field. comment field remarks to clarify the program go into comment field at the end of each line. comments must begin with a semicolon (;). each lines may be comment lines by beginning them with a semicolon. subroutines and large sections of a program generally begin with a comment block?serveral lines of comments that explain the general properties of the section of software that follows. special assembler symbols special assembler symbols are used for the register-specific addressing modes. these include a, r0 through r7, dptr, pc, c and ab. in addition, a dollar sign ($) can be used to refer to the current value of the location counter. some examples follow. setb c inc dptr jnb ti , $ the last instruction above makes effective use of asm51's location counter to avoid using a label. it could also be written as here: jnb ti , here indirect address for certain instructions, the operand field may specify a register that contains the address of the data. the commercial "at" sign (@) indicates address indirection and may only be used with r0, r1, the dptr, or the pc, depending on the instruction. for example, add a , @r0 movc a , @a+pc the first instruction above retrieves a byte of data from internal ram at the address specified in r0. the second instruction retrieves a byte of data from external code memory at the address formed by adding the contents of the accumulator to the program counter. note that the value of the program counter, when the add takes place, is the address of the instruction following movc. for both instruction above, the value retrieved is placed into the accumulator. immediate data instructions using immediate addressing provide data in the operand field that become part of the instruction. immediate data are preceded with a pound sign (#). for example, 136
constant equ 100 mov a , #0feh orl 40h , #constant all immediate data operations (except mov dptr,#data) require eight bits of data. the immediate data are evaluated as a 16-bit constant, and then the low-byte is used. all bits in the high-byte must be the same (00h or ffh) or the error message "value will not fit in a byte" is generated. for example, the following instructions are syntactically correct: mov a , #0ff00h mov a , #00ffh but the following two instructions generate error messages: mov a , #0fe00h mov a , #01ffh if signed decimal notation is used, constants from -256 to +255 may also be used. for example, the following two instructions are equivalent (and syntactically correct): mov a , #-256 mov a , #0ff00h both instructions above put 00h into accumulator a. data address many instructions access memory locations using direct addressing and require an on-chip data memory address (00h to 7fh) or an sfr address (80h to 0ffh) in the operand field. predefined symbols may be used for the sfr addresses. for example, mov a , 45h mov a , sbuf ;same as mov a, 99h bit address one of the most powerful features of the 8051 is the ability to access individual bits without the need for masking operations on bytes. instructions accessing bit-addressable locations must provide a bit address in internal data memory (00h to 7fh) or a bit address in the sfrs (80h to 0ffh). there are three ways to specify a bit address in an instruction: (a) explicitly by giving the address, (b) using the dot operator between the byte address and the bit position, and (c) using a predefined assembler symbol. some examples follow. setb 0e7h ;explicit bit address setb acc.7 ;dot operator (same as above) jnb ti , $ ;"ti" is a pre-defined symbol jnb 99h , $ ;(same as above) code address a code address is used in the operand field for jump instructions, including relative jumps (sjmp and conditional jumps), absolute jumps and calls (acall, ajmp), and long jumps and calls (ljmp, lcall). the code address is usually given in the form of a label. asm51 will determine the correct code address and insert into the instruction the correct 8-bit signed offset, 11-bit page address, or 16-bit long address, as appropriate. 137
generic jumps and calls asm51 allows programmers to use a generic jmp or call mnemonic. "jmp" can be used instead of sjmp, ajmp or ljmp; and "call" can be used instead of acall or lcall. the assembler converts the generic mnemonic to a "real" instruction following a few simple rules. the generic mnemonic converts to the short form (for jmp only) if no forward references are used and the jump destination is within -128 locations, or to the absolute form if no forward references are used and the instruction following the jmp or call instruction is in the same 2k block as the destination instruction. if short or absolute forms cannot be used, the conversion is to the long form. the conversion is not necessarily the best programming choice. for example, if branching ahead a few instrucions, the generic jmp will always convert to ljmp even though an sjmp is probably better. consider the following assembled instructions sequence using three generic jumps. loc obj line source 1234 1 org 1234h 1234 04 2 start: inc a 1235 80fd 3 jmp start ;assembles as sjmp 12fc 4 org start + 200 12fc 4134 5 jmp start ;assembles as ajmp 12fe 021301 6 jmp finish ;assembles as ljmp 1301 04 7 finish: inc a 8 end the first jump (line 3) assembles as sjmp because the destination is before the jump ( i.e., no forward reference) and the offset is less than -128. the org directive in line 4 creates a gap of 200 locations between the label start and the second jump, so the conversion on line 5 is to ajmp because the offset is too great for sjmp. note also that the address following the second jump (12feh) and the address of start (1234h) are within the same 2k page, which, for this instruction sequence, is bounded by 1000h and 17ffh. this criterion must be met for absolute addressing. the third jump assembles as ljmp because the destination (finish) is not yet defined when the jump is assembled (i.e., a forward reference is used). the reader can verify that the conversion is as stated by examining the object field for each jump instruction. assemble-time expression evaluation values and constants in the operand field may be expressed three ways: (a) explicitly (e.g.,0efh), (b) with a predefined symbol (e.g., acc), or (c) with an expression (e.g.,2 + 3). the use of expressions provides a powerful technique for making assembly language programs more readable and more flexible. when an expression is used, the assembler calculates a value and inserts it into the instruction. all expression calculations are performed using 16-bit arithmetic; however, either 8 or 16 bits are inserted into the instruction as needed. for example, the following two instructions are the same: mov dptr, #04ffh + 3 mov dptr, #0502h ;entire 16-bit result used if the same expression is used in a "mov a,#data" instruction, however, the error message "value will not fit in a byte" is generated by asm51. an overview of the rules for evaluateing expressions follows. 138
number bases the base for numeric constants is indicated in the usual way for intel microprocessors. constants must be followed with "b" for binary, "o" or "q" for octal, "d" or nothing for decimal, or "h" for hexadecimal. for example, the following instructions are the same: mov a , #15h mov a , #1111b mov a , #0fh mov a , #17q mov a , #15d note that a digit must be the first character for hexadecimal constants in order to differentiate them from labels (i.e., "0a5h" not "a5h"). charater strings strings using one or two characters may be used as operands in expressions. the ascii codes are converted to the binary equivalent by the assembler. character constants are enclosed in single quotes ('). some examples follow. cjne a , # 'q', again subb a , # '0' ;convert ascii digit to binary digit mov dptr, # 'ab' mov dptr, #4142h ;same as above arithmetic operators the arithmetic operators are + addition - subtraction * multiplication / division mod modulo (remainder after division) for example, the following two instructions are same: mov a, 10 +10h mov a, #1ah the following two instructions are also the same: mov a, #25 mod 7 mov a, #4 since the mod operator could be confused with a symbol, it must be seperated from its operands by at least one space or tab character, or the operands must be enclosed in parentheses. the same applies for the other operators composed of letters. logical operators the logical operators are or logical or and logical and xor logical exclusive or not logical not (complement) 139
the operation is applied on the corresponding bits in each operand. the operator must be separated from the operands by space or tab characters. for example, the following two instructions are the same: mov a, # '9' and 0fh mov a, #9 the not operator only takes one operand. the following three mov instructions are the same: three equ 3 minus_three equ -3 mov a, # (not three) + 1 mov a, #minus_three mov a, #11111 101b special operators the sepcial operators are shr shift right shl shift left high high-byte low low-byte () evaluate first for example, the following two instructions are the same: mov a, #8 shl 1 mov a, #10h the following two instructions are also the same: mov a, #high 1234h mov a, #12h relational operators when a relational operator is used between two operands, the result is alwalys false (0000h) or true (ffffh). the operators are eq = equals ne < > not equals lt < less than le <= less than or equal to gt > greater than ge >= greater than or equal to note that for each operator, two forms are acceptable (e.g., "eq" or "="). in the following examples, all relational tests are "true": mov a, #5 = 5 mov a,#5 ne 4 mov a,# 'x' lt 'z' mov a,# 'x' >= 'x' mov a,#$ > 0 mov a,#100 ge 50 140
so, the assembled instructions are equal to mov a, #0ffh even though expressions evaluate to 16-bit results (i.e., 0ffffh), in the examples above only the low-order eight bits are used, since the instruction is a move byte operation. the result is not considered too big in this case, because as signed numbers the 16-bit value ffffh and the 8-bit value ffh are the same (-1). expression examples the following are examples of expressions and the values that result: expression result 'b' - 'a' 0001h 8/3 0002h 155 mod 2 0001h 4 * 4 0010h 8 and 7 0000h not 1 fffeh 'a' shl 8 4100h low 65535 00ffh (8 + 1) * 2 0012h 5 eq 4 0000h 'a' lt 'b' ffffh 3 <= 3 ffffhss a practical example that illustrates a common operation for timer initialization follows: put -500 into timer 1 registers th1 and tl1. in using the high and low operators, a good approach is value equ -500 mov th1, #high value mov tl1, #low value the assembler converts -500 to the corresponding 16-bit value (fe0ch); then the high and low operators extract the high (feh) and low (0ch) bytes. as appropriate for each mov instruction. operator precedence the precedence of expression operators from highest to lowest is ( ) high low * / mod shl shr + - eq ne lt le gt ge = < > < <= > >= not and or xor when operators of the same precedence are used, they are evaluated left to right. examples: expression value high ( 'a' shl 8) 0041h high 'a' shl 8 0000h not 'a' - 1 ffbfh 'a' or 'a' shl 8 4141h 141
assembler directives assembler directives are instructions to the assembler program. they are not assembly language instructions executable by the target microprocessor. however, they are placed in the mnemonic field of the program. with the exception of db and dw, they have no direct effect on the contents of memory. asm51 provides several catagories of directives: assembler state control (org, end, using) symbol definition (segment, equ, set, data, idata, xdata, bit, code) storage initialization/reservation (ds, dbit, db, dw) program linkage (public, extrn,name) segment selection (rseg, cseg, dseg, iseg, eseg, xseg) ? ? ? ? ? each assembler directive is presented below, ordered by catagory. assembler state control org (set origin) the format for the org (set origin) directive is org expression the org directive alters the location counter to set a new program origin for statements that follow. a label is not permitted. two examples follow. org 100h ;set location counter to 100h org ($ + 1000h) and 0f00h ;set to next 4k boundary the org directive can be used in any segment type. if the current segment is absolute, the value will be an absolute address in the current segment. if a relocatable segment is active, the value of the org expression is treated as an offset from the base address of the current instance of the segment. end the format of the end directive is end end should be the last statement in the source file. no label is permitted and nothing beyond the end statement is processed by the assembler. using the format of the end directive is using expression this directive informs asm51 of the currently active register bank. subsequent uses of the predefined symbolic register addresses ar0 to ar7 will convert to the appropriate direct address for the active register bank. consider the following sequence: using 3 push ar7 using 1 push ar7 the first push above assembles to push 1fh (r7 in bank 3), whereas the second push assembles to push 0fh (r7 in bank 1). note that using does not actually switch register banks; it only informs asm51 of the active bank. executing 8051 instructions is the only way to switch register banks. this is illustrated by modifying the example above as follows: 142
mov psw, #00011000b ;select register bank 3 using 3 push ar7 ;assemble to push 1fh mov psw, #00001000b ;select register bank 1 using 1 push ar7 ;assemble to push 0fh symbol definition the symbol definition directives create symbols that represent segment, registers, numbers, and addresses. none of these directives may be preceded by a label. symbols defined by these directives may not have been previously defined and may not be redefined by any means. the set directive is the only exception. symbol definiton directives are described below. segment the format for the segment directive is shown below. symbol segment segment_type the symbol is the name of a relocatable segment. in the use of segments, asm51 is more complex than conventional assemblers, which generally support only "code" and "data" segment types. however, asm51 defines additional segment types to accommodate the diverse memory spaces in the 8051. the following are the defined 8051 segment types (memory spaces): code (the code segment) xdata (the external data space) data (the internal data space accessible by direct addressing, 00h?07h) idata (the entire internal data space accessible by indirect addressing, 00h?07h) bit (the bit space; overlapping byte locations 20h?2fh of the internal data space) ? ? ? ? ? for example, the statement eprom segment code declares the symbol eprom to be a segment of type code. note that this statement simply declares what eprom is. to actually begin using this segment, the rseg directive is used (see below). equ (equate) the format for the equ directive is symbol equ expression the equ directive assigns a numeric value to a specified symbol name. the symbol must be a valid symbol name, and the expression must conform to the rules described earlier. the following are examples of the equ directive: n27 equ 27 ;set n27 to the value 27 here equ $ ;set "here" to the value of ;the location counter cr equ 0dh ;set cr (carriage return) to 0dh message: db 'this is a message' length equ $ - message ;"length" equals length of "message" other symbol definition directives the set directive is similar to the equ directive except the symbol may be redefined later, using another set directive. 143
the data, idata, xdata, bit, and code directives assign addresses of the corresponding segment type to a symbol. these directives are not essential. a similar effect can be achieved using the equ directive; if used, however, they evoke powerful type-checking by asm51. consider the following two directives and four instructions: flag1 equ 05h flag2 bit 05h setb flag1 setb flag2 mov flag1, #0 mov flag2, #0 the use of flag2 in the last instruction in this sequence will generate a "data segment address expected" error message from asm51. since flag2 is defined as a bit address (using the bit directive), it can be used in a set bit instruction, but it cannot be used in a move byte instruction. hence, the error. even though flag1 represents the same value (05h), it was defined using equ and does not have an associated address space. this is not an advantage of equ, but rather, a disadvantage. by properly defining address symbols for use in a specific memory space (using the directives bit, data, xdata,ect.), the programmer takes advantage of asm51's powerful type-checking and avoids bugs from the misuse of symbols. storage initialization/reservation the storage initialization and reservation directives initialize and reserve space in either word, byte, or bit units. the space reserved starts at the location indicated by the current value of the location counter in the currently active segment. these directives may be preceded by a label. the storage initialization/reservation directives are described below. ds (define storage) the format for the ds (define storage) directive is [label:] ds expression the ds directive reserves space in byte units. it can be used in any segment type except bit. the expression must be a valid assemble-time expression with no forward references and no relocatable or external references. when a ds statement is encountered in a program, the location counter of the current segment is incremented by the value of the expression. the sum of the location counter and the specified expression should not exceed the limitations of the current address space. the following statement create a 40-byte buffer in the internal data segment: dseg at 30h ;put in data segment (absolute, internal) length equ 40 buffer: ds lengrh ;40 bytes reserved the label buffer represents the address of the first location of reserved memory. for this example, the buffer begins at address 30h because "at 30h" is specified with dseg. the buffer could be cleared using the following instruction sequence: mov r7, #length mov r0, #buffer loop: mov @r0, #0 djnz r7, loop (continue) 144
to create a 1000-byte buffer in external ram starting at 4000h, the following directives could be used: xstart equ 4000h xlength equ 1000 xseg at xstart xbuffer: ds xlength this buffer could be cleared with the following instruction sequence: mov dptr, #xbuffer loop: clr a movx @dptr, a inc dptr mov a, dpl cjne a, #low (xbuffer + xlength + 1), loop mov a, dph cjne a, #high (xbuffer + xlength + 1), loop (continue) this is an excellent example of a powerful use of asm51's operators and assemble-time expressions. since an instruction does not exist to compare the data pointer with an immediate value, the operation must be fabricated from available instructions. two compares are required, one each for the high- and low-bytes of the dptr. furthermore, the compare-and-jump-if-not-equal instruction works only with the accumulator or a register, so the data pointer bytes must be moved into the accumulator before the cjne instruction. the loop terminates only when the data pointer has reached xbuffer + length + 1. (the "+1" is needed because the data pointer is incremented after the last movx instruction.) dbit the format for the dbit (define bit) directive is, [label:] dbit expression the dbit directive reserves space in bit units. it can be used only in a bit segment. the expression must be a valid assemble-time expression with no forward references. when the dbit statement is encountered in a program, the location counter of the current (bit) segment is incremented by the value of the expression. note that in a bit segment, the basic unit of the location counter is bits rather than bytes. the following directives creat three flags in a absolute bit segment: bseg ;bit segment (absolute) keflag: dbit 1 ;keyboard status prflag: dbit 1 ;printer status dkflag: dbit 1 ;disk status since an address is not specified with bseg in the example above, the address of the flags defined by dbit could be determined (if one wishes to to so) by examining the symbol table in the .lst or .m51 files. if the definitions above were the first use of bseg, then kbflag would be at bit address 00h (bit 0 of byte address 20h). if other bits were defined previously using bseg, then the definitions above would follow the last bit defined. db (define byte) the format for the db (define byte) directive is, [label:] db expression [, expression] [?] the db directive initializes code memory with byte values. since it is used to actually place data constants in code memory, a code segment must be active. the expression list is a series of one or more byte values (each of which may be an expression) separated by commas. 145
the db directive permits character strings (enclosed in single quotes) longer than two characters as long as they are not part of an expression. each character in the string is converted to the corresponding ascii code. if a label is used, it is assigned the address of th first byte. for example, the following statements cseg at 0100h squares: db 0, 1, 4, 9, 16, 25 ;squares of numbers 0-5 message: db 'login:', 0 ;null-terminated character string when assembled, result in the following hexadecimal memory assignments for external code memory: address contents 0100 00 0101 01 0102 04 0103 09 0104 10 0105 19 0106 4c 0107 6f 0108 67 0109 69 010a 6e 010b 3a 010c 00 dw (define word) the format for the dw (define word) directive is [label:] dw expression [, expression] [?] the dw directive is the same as the db directive except two memory locations (16 bits) are assigned for each data item. for example, the statements cseg at 200h dw $, 'a', 1234h, 2, 'bc' result in the following hexadecimal memory assignments: address contents 0200 02 0201 00 0202 00 0203 41 0204 12 0205 34 0206 00 0207 02 0208 42 0209 43 program linkage program linkage directives allow the separately assembled modules (files) to communicate by permitting intermodule references and the naming of modules. in the following discussion, a "module" can be considered a "file." (in fact, a module may encompass more than one file.) 146
public the format for the public (public symbol) directive is public symbol [, symbol] [?] the public directive allows the list of specified symbols to known and used outside the currently assembled module. a symbol declared public must be defined in the current module. declaring it public allows it to be referenced in another module. for example, public inchar, outchr, inline, outstr extrn the format for the extrn (external symbol) directive is extrn segment_type (symbol [, symbol] [?], ?) the extrn directive lists symbols to be referenced in the current module that are defined in other modules. the list of external symbols must have a segment type associated with each symbol in the list. (the segment types are code, xdata, data, idata, bit, and number. number is a type-less symbol defined by equ.) the segment type indicates the way a symbol may be used. the information is important at link-time to ensure symbols are used properly in different modules. the public and extrn directives work together. consider the two files, main.src and messages. src. the subroutines hello and good_bye are defined in the module messages but are made available to other modules using the public directive. the subroutines are called in the module main even though they are not defined there. the extrn directive declares that these symbols are defined in another module. main.src: extrn code (hello, good_bye) ? call hello ? call good_bye ? end messages.src: public hello, good_bye ? hello: (begin subroutine) ? ret good_bye: (begin subroutine) ? ret ? end neither main.src nor messages.src is a complete program; they must be assembled separately and linked together to form an executable program. during linking, the external references are resolved with correct addresses inserted as the destination for the call instructions. name the format for the name directive is name module_name 147
all the usual rules for symbol names apply to module names. if a name is not provided, the module takes on the file name (without a drive or subdirectory specifier and without an extension). in the absence of any use of the name directive, a program will contain one module for each file. the concept of "modules," therefore, is somewhat cumbersome, at least for relatively small programming problems. even programs of moderate size (encompassing, for example, several files complete with relocatable segments) needn't use the name directive and needn't pay any special attention to the concept of "modules." for this reason, it was mentioned in the definition that a module may be considered a "file," to simplify learning asm51. however, for very large programs (several thousand lines of code, or more), it makes sense to partition the problem into modules, where, for example, each module may encompass several files containing routines having a common purpose. segment selection directives when the assembler encounters a segment selection directive, it diverts the following code or data into the selected segment until another segment is selected by a segment selection directive. the directive may select may select a previously defined relocatable segment or optionally create and select absolute segments. rseg (relocatable segment) the format for the rseg (relocatable segment) directive is rseg segment_name where "segment_name" is the name of a relocatable segment previously defined with the segment directive. rseg is a "segment selection" directive that diverts subsequent code or data into the named segment until another segment selection directive is encountered. selecting absolute segments rseg selects a relocatable segment. an "absolute" segment, on the other hand, is selected using one of the directives: cseg (at address) dseg (at address) iseg (at address) bseg (at address) xseg (at address) these directives select an absolute segment within the code, internal data, indirect internal data, bit, or external data address spaces, respectively. if an absolute address is provided (by indicating "at address"), the assembler terminates the last absolute address segment, if any, of the specified segment type and creates a new absolute segment starting at that address. if an absolute address is not specified, the last absolute segment of the specified type is continuted. if no absolute segment of this type was previously selected and the absolute address is omitted, a new segment is created starting at location 0. forward references are not allowed and start addresses must be absolute. each segment has its own location counter, which is always set to 0 initially. the default segment is an absolute code segment; therefore, the initial state of the assembler is location 0000h in the absolute code segment. when another segment is chosen for the first time, the location counter of the former segment retains the last active value. when that former segment is reselected, the location counter picks up at the last active value. the org directive may be used to change the location counter within the currently selected segment. assembler controls assembler controls establish the format of the listing and object files by regulating the actions of asm51. for the most part, assembler controls affect the look of the listing file, without having any affect on the program itself. they can be entered on the invocation line when a program is assembled, or they can be placed in the source file. assembler controls appearing in the source file must be preceded with a dollor sign and must begin in column 1. 148
there are two categories of assembler controls: primary and general. primary controls can be placed in the invocation line or at the beginnig of the source program. only other primary controls may precede a primary control. general controls may be placed anywhere in the source program. linker operation in developing large application programs, it is common to divide tasks into subprograms or modules containing sections of code (usually subroutines) that can be written separately from the overall program. the term "modular programming" refers to this programming strategy. generally, modules are relocatable, meaning they are not intended for a specific address in the code or data space. a linking and locating program is needed to combine the modules into one absolute object module that can be executed. intel's rl51 is a typical linker/locator. it processes a series of relocatable object modules as input and creates an executable machine language program (program, perhaps) and a listing file containing a memory map and symbol table (program.m51). this is illustrated in following figure. file3.obj file2.obj file1.obj rl51 program.abs program.map linker operation legend utility program user file as relocatable modules are combined, all values for external symbols are resolved with values inserted into the output file. the linker is invoked from the system prompt by rl51 input_list [t0 output_file] [location_controls] the input_list is a list of relocatable object modules (files) separated by commas. the output_list is the name of the output absolute object module. if none is supplied, it defaults to the name of the first input file without any suffix. the location_controls set start addresses for the named segments. for example, suppose three modules or files (main.obj, messages.obj, and subroutines.obj) are to be combined into an executable program (example), and that these modules each contain two relocatable segments, one called eprom of type code, and the other called onchip of type data. suppose further that the code segment is to be executable at address 4000h and the data segment is to reside starting at address 30h (in internal ram). the following linker invocation could be used: rs51 main.obj, messages.obj, subroutines.obj to example & code (eprom (4000h) data (onchip (30h)) note that the ampersand character "&" is used as the line continuaton character. if the program begins at the label start, and this is the first instruction in the main module, then execution begins at address 4000h. if the main module was not linked first, or if the label start is not at the beginning of main, then the program's entry point can be determined by examining the symbol table in the listing file example.m51 created by rl51. by default, example.m51 will contain only the link map. if a symbol table is desired, then each source program must have used the sdebug control. the following table shows the assembler controls supported by asm51. 149
assembler controls supported by asm51 name primary/ general default abbrev. meaning date (date) p date( ) da place string in header (9 char. max.) debug p nodebug db outputs debug symbol information to object file eject g not applicable ej continue listing on next page errorprint (file) p noerrorprint ep designates a file to receive error messages in addition to the listing file (defauts to console) noerrorprint p noerrorprint noep designates that error messages will be printed in listing file only gen g genonly go list only the fully expanded source as if all lines generated by a macro call were already in the source file genonly g genonly noge list only the original source text in the listing file inclued(file) g not applicable ic designates a file to be included as part of the program list g list li print subsequent lines of source code in listing file nolist g list noli do not print subsequent lines of source code in lisitng file macro (men_precent) p macro(50) mr evaluate and expand all macro calls. allocate percentage of free memory for macro processing nomacro p macro(50) nomr do not evalutate macro calls mod51 p mod51 mo rec ognize the 8051-specific predefined special function registers nomod51 p mod51 nomo do not rec ognize the 8051-specific predefined special function registers object(file) p object(source.obj) oj designates file to receive object code noobject p object(source.obj) nooj designates that no object file will be created paging p paging pi designates that listing file be broken into pages and each will have a header nopaging p paging nopi designates that listing file will contain no page breaks pagelength (n) p pagelengt(60) pl sets maximun number of lines in each page of listing file (range=10 to 65536) page width (n) p pagewidth(120) pw set maximum number of char acters in each line of listing file (range = 72 to 132) print(file) p print(source.lst) pr designates file to receive source listing noprint p print(source.lst) nopr designates that no listing file will be created save g not applicable sa stores current control settings from save stack restore g not applicable rs restores control settings from save stack registerbank (rb,...) p registerbank(0) rb indicates one or more banks used in program module noregister- bank p registerbank(0) norb indicates that no register banks are used symbols p symbols sb creates a formatted table of all symbols used in program nosymbols p symbols nosb designates that no symbol table is created title(string) g title( ) tt places a string in all subsequent page headers (max.60 characters) workfiles (path) p same as source wf designates alternate path for temporay workfiles xref p noxref xr creates a cross reference listing of all symbols used in program noxref p noxref noxr designates that no cross reference list is created 150
macros the macro processing facility (mpl) of asm51 is a "string replacement" facility. macros allow frequently used sections of code be defined once using a simple mnemonic and used anywhere in the program by inserting the mnemonic. programming using macros is a powerful extension of the techniques described thus far. macros can be defined anywhere in a source program and subsequently used like any other instruction. the syntax for macro definition is %*define (call_pattern) (macro_body) once defined, the call pattern is like a mnemonic; it may be used like any assembly language instruction by placing it in the mnemonic field of a program. macros are made distinct from "real" instructions by preceding them with a percent sign, "%". when the source program is assembled, everything within the macro-body, on a character-by-character basis, is substituted for the call-pattern. the mystique of macros is largely unfounded. they provide a simple means for replacing cumbersome instruction patterns with primitive, easy-to-remember mnemonics. the substitution, we reiterate, is on a character-by-character basis?nothing more, nothing less. for example, if the following macro definition appears at the beginning of a source file, %*define (push_dptr) (push dph push dpl ) then the statement %push_dptr will appear in the .lst file as push dph push dpl the example above is a typical macro. since the 8051 stack instructions operate only on direct addresses, pushing the data pointer requires two push instructions. a similar macro can be created to pop the data pointer. there are several distinct advantages in using macros: a source program using macros is more readable, since the macro mnemonic is generally more indicative of the intended operation than the equivalent assembler instructions. the source program is shorter and requires less typing. using macros reduces bugs using macros frees the programmer from dealing with low-level details. the last two points above are related. once a macro is written and debugged, it is used freely without the worry of bugs. in the push_dptr example above, if push and pop instructions are used rather than push and pop macros, the programmer may inadvertently reverse the order of the pushes or pops. (was it the high-byte or low- byte that was pushed first?) this would create a bug. using macros, however, the details are worked out once? when the macro is written?and the macro is used freely thereafter, without the worry of bugs. since the replacement is on a character-by-character basis, the macro definition should be carefully constructed with carriage returns, tabs, ect., to ensure proper alignment of the macro statements with the rest of the assembly language program. some trial and error is required. there are advanced features of asm51's macro-processing facility that allow for parameter passing, local labels, repeat operations, assembly flow control, and so on. these are discussed below. ? ? ? ? 151
parameter passing a macro with parameters passed from the main program has the following modified format: %*define (macro_name (parameter_list)) (macro_body) for example, if the following macro is defined, %*define (cmpa# (value)) (cjne a, #%value, $ + 3 ) then the macro call %cmpa# (20h) will expand to the following instruction in the .lst file: cjne a, #20h, $ + 3 although the 8051 does not have a "compare accumulator" instruction, one is easily created using the cjne instruction with "$+3" (the next instruction) as the destination for the conditional jump. the cmpa# mnemonic may be easier to remember for many programmers. besides, use of the macro unburdens the programmer from remembering notational details, such as "$+3." let's develop another example. it would be nice if the 8051 had instructions such as jump if accumulator greater than x jump if accumulator greater than or equal to x jump if accumulator less than x jump if accumulator less than or equal to x but it does not. these operations can be created using cjne followed by jc or jnc, but the details are tricky. suppose, for example, it is desired to jump to the label greater_than if the accumulator contains an ascii code greater than "z" (5ah). the following instruction sequence would work: cjne a, #5bh, $3 jnc greater_than the cjne instruction subtracts 5bh (i.e., "z" + 1) from the content of a and sets or clears the carry flag accordingly. cjne leaves c=1 for accumulator values 00h up to and including 5ah. (note: 5ah-5bh<0, therefore c=1; but 5bh-5bh=0, therefore c=0.) jumping to greater_than on the condition "not carry" correctly jumps for accumulator values 5bh, 5ch, 5dh, and so on, up to ffh. once details such as these are worked out, they can be simplified by inventing an appropriate mnemonic, defining a macro, and using the macro instead of the corresponding instruction sequence. here's the definition for a "jump if greater than" macro: %*define (jgt (value, label)) (cjne a, #%value+1, $+3 ;jgt jnc %label ) to test if the accumulator contains an ascii code greater than "z," as just discussed,the macro would be called as %jgt ('z', greater_than) asm51 would expand this into cjne a, #5bh, $+3 ;jgt jnc greater_than the jgt macro is an excellent example of a relevant and powerful use of macros. by using macros, the programmer benefits by using a meaningful mnemonic and avoiding messy and potentially bug-ridden details. 152
local labels local labels may be used within a macro using the following format: %*define (macro_name [(parameter_list)]) [local list_of_local_labels] (macro_body) for example, the following macro definition %*define (dec_dptr) local skip (dec dpl ;decrement data pointer mov a, dpl cjne a, #0ffh, %skip dec dpl %skip: ) would be called as %dec_dptr and would be expanded by asm51 into dec dpl ;decrement data pointer mov a, dpl cjne a, #0ffh, skip00 dec dph skip00: note that a local label generally will not conflict with the same label used elsewhere in the source program, since asm51 appends a numeric code to the local label when the macro is expanded. furthermore, the next use of the same local label receives the next numeric code, and so on. the macro above has a potential "side effect." the accumulator is used as a temporary holding place for dpl. if the macro is used within a section of code that uses a for another purpose, the value in a would be lost. this side effect probably represents a bug in the program. the macro definition could guard against this by saving a on the stack. here's an alternate definition for the dec_dptr macro: %*define (dec_dptr) local skip (pushacc dec dpl ;decrement data pointer mov a, dpl cjne a, #0ffh, %skip dec dph %skip: pop acc ) repeat operations this is one of several built-in (predefined) macros. the format is %repeat (expression) (text) for example, to fill a block of memory with 100 nop instructions, %repeat (100) (nop ) 153
control flow operations the conditional assembly of section of code is provided by asm51's control flow macro definition. the format is %if (expression) then (balanced_text) [else (balanced_text)] fi for example, intrenal equ 1 ;1 = 8051 serial i/o drivers ;0 = 8251 serial i/o drivers . . %if (internal) then (inchar: . ;8051 drivers . outchr: . . ) else (inchar: . ;8251 drivers . outchr: . . ) in this example, the symbol internal is given the value 1 to select i/o subroutines for the 8051's serial port, or the value 0 to select i/o subroutines for an external uart, in this case the 8251. the if macro causes asm51 to assemble one set of drivers and skip over the other. elsewhere in the program, the inchar and outchr subroutines are used without consideration for the particular hardware configuration. as long as the program as assembled with the correct value for internal, the correct subroutine is executed. 154
appendix b: 8051 c programming advantages and disadvantages of 8051 c the advantages of programming the 8051 in c as compared to assembly are: offers all the benefits of high-level, structured programming languages such as c, including the ease of writing subroutines often relieves the programmer of the hardware details that the complier handles on behalf of the programmer easier to write, especially for large and complex programs produces more readable program source codes nevertheless, 8051 c, being very similar to the conventional c language, also suffers from the following disadvantages: processes the disadvantages of high-level, structured programming languages. generally generates larger machine codes programmer has less control and less ability to directly interact with hardware to compare between 8051 c and assembly language, consider the solutions to the example?write a program using timer 0 to create a 1khz square wave on p1.0. a solution written below in 8051 c language: sbit portbit = p1^0; /*use variable portbit to refer to p1.0*/ main ( ) { tmod = 1; while (1) { th0 = 0xfe; tl0 = 0xc; tr0 = 1; while (tf0 !=1); tr0 = 0; tf0 = 0; portbit = !(p1.^0); } } a solution written below in assembly language: org 8100h mov tmod, #01h ;16-bit timer mode loop: mov th0, #0feh ;-500 (high byte) mov tl0, #0ch ;-500 (low byte) setb tr0 ;start timer wait: jnb tf0, wait ;wait for overflow clr tr0 ;stop timer clr tf0 ;clear timer overflow flag cpl p1.0 ;toggle port bit sjmp loop ;repeat end ? ? ? ? ? ? ? 155
notice that both the assembly and c language solutions for the above example require almost the same number of lines. however, the difference lies in the readability of these programs. the c version seems more human than assembly, and is hence more readable. this often helps facilitate the human programmer's efforts to write even very complex programs. the assembly language version is more closely related to the machine code, and though less readable, often results in more compact machine code. as with this example, the resultant machine code from the assembly version takes 83 bytes while that of the c version requires 149 bytes, an increase of 79.5%! the human programmer's choice of either high-level c language or assembly language for talking to the 8051, whose language is machine language, presents an interesting picture, as shown in following figure. human language eg. english, malay, chinese machine language eg. 10011101 0101010101 complier assembler c (high-level) language eg. for (x=0; x<9; x++)... assembly language eg. mov, add, sub conversion between human, high-level, assembly, and machine language 8051 c compilers we saw in the above figure that a complier is needed to convert programs written in 8051 c language into machine language, just as an assembler is needed in the case of programs written in assembly language. a complier basically acts just like an assembler, except that it is more complex since the difference between c and machine language is far greater than that between assembly and machine language. hence the complier faces a greater task to bridge that difference. currently, there exist various 8051 c complier, which offer almost similar functions. all our examples and programs have been compiled and tested with keil's vision 2 ide by keil software, an integrated 8051 program development envrionment that includes its c51 cross compiler for c. a cross compiler is a compiler that normally runs on a platform such as ibm compatible pcs but is meant to compile programs into codes to be run on other platforms such as the 8051. data types 8051 c is very much like the conventional c language, except that several extensions and adaptations have been made to make it suitable for the 8051 programming environment. the first concern for the 8051 c programmer is the data types. recall that a data type is something we use to store data. readers will be familiar with the basic c data types such as int, char, and float, which are used to create variables to store integers, characters, or floating- points. in 8051 c, all the basic c data types are supported, plus a few additional data types meant to be used specifically with the 8051. the following table gives a list of the common data types used in 8051 c. the ones in bold are the specific 8051 extensions. the data type bit can be used to declare variables that reside in the 8051's bit-addressable locations (namely byte locations 20h to 2fh or bit locations 00h to 7fh). obviously, these bit variables can only store bit values of either 0 or 1. as an example, the following c statement: bit flag = 0; declares a bit variable called flag and initializes it to 0. 156
data types used in 8051 c language data type bits bytes value range bit 1 0 to 1 signed char 8 1 -128 to +127 unsigned char 8 1 0 to 255 enum 16 2 -32768 to +32767 signed short 16 2 -32768 to +32767 unsigned short 16 2 0 to 65535 signed int 16 2 -32768 to +32767 unsigned int 16 2 0 to 65535 signed long 32 4 -2,147,483,648 to +2,147,483,647 unsigned long 32 4 0 to 4,294,967,295 float 32 4 1.175494e-38 to 3.402823e+38 sbit 1 0 to 1 sfr 8 1 0 to 255 sfr16 16 2 0 to 65535 the data type sbit is somewhat similar to the bit data type, except that it is normally used to declare 1-bit variables that reside in special function registes (sfrs). for example: sbit p = 0xd0; declares the sbit variable p and specifies that it refers to bit address d0h, which is really the lsb of the psw sfr. notice the difference here in the usage of the assignment ("=") operator. in the context of sbit declarations, it indicatess what address the sbit variable resides in, while in bit declarations, it is used to specify the initial value of the bit variable. besides directly assigning a bit address to an sbit variable, we could also use a previously defined sfr variable as the base address and assign our sbit variable to refer to a certain bit within that sfr . for example: sfr psw = 0xd0; sbit p = psw^0; this declares an sfr variable called psw that refers to the byte address d0h and then uses it as the base address to refer to its lsb (bit 0). this is then assigned to an sbit variable, p. for this purpose, the carat symbol (^) is used to specify bit position 0 of the psw. a third alternative uses a constant byte address as the base address within which a certain bit is referred. as an illustration, the previous two statements can be replaced with the following: sbit p = 0xd0 ^ 0; meanwhile, the sfr data type is used to declare byte (8-bit) variables that are associated with sfrs. the statement: sfr ie = 0xa8; declares an sfr variable ie that resides at byte address a8h. recall that this address is where the interrupt enable (ie) sfr is located; therefore, the sfr data type is just a means to enable us to assign names for sfrs so that it is easier to remember. the sfr16 data type is very similar to sfr but, while the sfr data type is used for 8-bit sfrs, sfr16 is used for 16-bit sfrs. for example, the following statement: sfr16 dptr = 0x82; 157
declares a 16-bit variable dptr whose lower-byte address is at 82h. checking through the 8051 architecture, we find that this is the address of the dpl sfr, so again, the sfr16 data type makes it easier for us to refer to the sfrs by name rather than address. there's just one thing left to mention. when declaring sbit , sfr , or sfr16 variables, remember to do so outside main, otherwise you will get an error. in actual fact though, all the sfrs in the 8051, including the individual flag, status, and control bits in the bit-addressable sfrs have already been declared in an include file, called reg51.h, which comes packaged with most 8051 c compilers. by using reg51.h, we can refer for instance to the interrupt enable register as simply ie rather than having to specify the address a8h, and to the data pointer as dptr rather than 82h. all this makes 8051 c programs more human-readable and manageable. the contents of reg51.h are listed below. /*-------------------------------------------------------------------------------------------------------------------- reg51.h header file for generic 8051 microcontroller. -----------------------------------------------------------------------------------------------------------------------*/ sbit ie1 = 0x8b; sbit it1 = 0x8a; sbit ie0 = 0x89; sbit it0 = 0x88; /* ie */ sbit ea = 0xaf; sbit es = 0xac; sbit et1 = 0xab; sbit ex1 = 0xaa; sbit et0 = 0xa9; sbit ex0 = 0xa8; /* ip */ sbit ps = 0xbc; sbit pt1 = 0xbb; sbit px1 = 0xba; sbit pt0 = 0xb9; sbit px0 = 0xb8; /* p3 */ sbit rd = 0xb7; sbit wr = 0xb6; sbit t1 = 0xb5; sbit t0 = 0xb4; sbit int1 = 0xb3; sbit int0 = 0xb2; sbit txd = 0xb1; sbit rxd = 0xb0; /* scon */ sbit sm0 = 0x9f; sbit sm1 = 0x9e; sbit sm2 = 0x9d; sbit ren = 0x9c; sbit tb8 = 0x9b; sbit rb8 = 0x9a; sbit ti = 0x99; sbit ri = 0x98; /* byte register */ sfr p0 = 0x80; sfr p1 = 0x90; sfr p2 = 0xa0; sfr p3 = 0xb0; sfr psw = 0xd0; sfr acc = 0xe0; sfr b = 0xf0; sfr sp = 0x81; sfr dpl = 0x82; sfr dph = 0x83; sfr pcon = 0x87; sfr tcon = 0x88; sfr tmod = 0x89; sfr tl0 = 0x8a; sfr tl1 = 0x8b; sfr th0 = 0x8c; sfr th1 = 0x8d; sfr ie = 0xa8; sfr ip = 0xb8; sfr scon = 0x98; sfr sbuf = 0x99; /* bit register */ /* psw */ sbit cy = 0xd7; sbit ac = 0xd6; sbit f0 = 0xd5; sbit rs1 = 0xd4; sbit rs0 = 0xd3; sbit ov = 0xd2; sbit p = 0xd0; /* tcon */ sbit tf1 = 0x8f; sbit tr1 = 0x8e; sbit tf0 = 0x8d; sbit tr0 = 0x8c; 158
memory types and models the 8051 has various types of memory space, including internal and external code and data memory. when declaring variables, it is hence reasonable to wonder in which type of memory those variables would reside. for this purpose, several memory type specifiers are available for use, as shown in following table. memory types used in 8051 c language memory type description (size) code code memory (64 kbytes) data directly addressable internal data memory (128 bytes) idata indirectly addressable internal data memory (256 bytes) bdata bit-addressable internal data memory (16 bytes) xdata external data memory (64 kbytes) pdata paged external data memory (256 bytes) the first memory type specifier given in above table is code . this is used to specify that a variable is to reside in code memory, which has a range of up to 64 kbytes. for example: char code errormsg[ ] = "an error occurred" ; declares a char array called errormsg that resides in code memory. if you want to put a variable into data memory, then use either of the remaining five data memory specifiers in above table. though the choice rests on you, bear in mind that each type of data memory affect the speed of access and the size of available data memory. for instance, consider the following declarations: signed int data num1; bit bdata numbit; unsigned int xdata num2; the first statement creates a signed int variable num1 that resides in inernal data memory (00h to 7fh). the next line declares a bit variable numbit that is to reside in the bit-addressable memory locations (byte addresses 20h to 2fh), also known as bdata . finally, the last line declares an unsigned int variable called num2 that resides in external data memory, xdata . having a variable located in the directly addressable internal data memory speeds up access considerably; hence, for programs that are time-critical, the variables should be of type data . for other variants such as 8052 with internal data memory up to 256 bytes, the idata specifier may be used. note however that this is slower than data since it must use indirect addressing. meanwhile, if you would rather have your variables reside in external memory, you have the choice of declaring them as pdata or xdata . a variable declared to be in pdata resides in the first 256 bytes (a page) of external memory, while if more storage is required, xdata should be used, which allows for accessing up to 64 kbytes of external data memory. what if when declaring a variable you forget to explicitly specify what type of memory it should reside in, or you wish that all variables are assigned a default memory type without having to specify them one by one? in this case, we make use of memory models . the following table lists the various memory models that you can use. memory models used in 8051 c language memory model description small variables default to the internal data memory (data) compact variables default to the first 256 bytes of external data memory (pdata) large variables default to external data memory (xdata) 159
a program is explicitly selected to be in a certain memory model by using the c directive, #pragma. otherwise, the default memory model is small . it is recommended that programs use the small memory model as it allows for the fastest possible access by defaulting all variables to reside in internal data memory. the compact memory model causes all variables to default to the first page of external data memory while the large memory model causes all variables to default to the full external data memory range of up to 64 kbytes. arrays often, a group of variables used to store data of the same type need to be grouped together for better readability. for example, the ascii table for decimal digits would be as shown below. ascii table for decimal digits decimal digit ascii code in hex 0 30h 1 31h 2 32h 3 33h 4 34h 5 35h 6 36h 7 37h 8 38h 9 39h to store such a table in an 8051 c program, an array could be used. an array is a group of variables of the same data type, all of which could be accessed by using the name of the arrary along with an appropriate index. the array to store the decimal ascii table is: int table [10] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39}; notice that all the elements of an array are separated by commas. to access an individul element, an index starting from 0 is used. for instance, table[0] refers to the first element while table[9] refers to the last element in this ascii table. structures sometime it is also desired that variables of different data types but which are related to each other in some way be grouped together. for example, the name, age, and date of birth of a person would be stored in different types of variables, but all refer to the person's personal details. in such a case, a structure can be declared. a structure is a group of related variables that could be of different data types. such a structure is declared by: struct person { char name; int age; long dob; }; once such a structure has been declared, it can be used like a data type specifier to create structure variables that have the member's name, age, and dob. for example: struct person grace = {"grace", 22, 01311980}; 160
would create a structure variable grace to store the name, age, and data of birth of a person called grace. then in order to access the specific members within the person structure variable, use the variable name followed by the dot operator (.) and the member name. therefore, grace.name, grace.age, grace.dob would refer to grace's name, age, and data of birth, respectively. pointers when programming the 8051 in assembly, sometimes register such as r0, r1, and dptr are used to store the addresses of some data in a certain memory location. when data is accessed via these registers, indirect addressing is used. in this case, we say that r0, r1, or dptr are used to point to the data, so they are essentially pointers. correspondingly in c, indirect access of data can be done through specially defined pointer variables. point- ers are simply just special types of variables, but whereas normal variables are used to directly store data, pointer variables are used to store the addresses of the data. just bear in mind that whether you use normal variables or pointer variables, you still get to access the data in the end. it is just whether you go directly to where it is stored and get the data, as in the case of normal variables, or first consult a directory to check the location of that data before going there to get it, as in the case of pointer variables. declaring a pointer follows the format: data_type *pointer_name; where data_type refers to which type of data that the pointer is pointing to * denotes that this is a pointer variable pointer_name is the name of the pointer as an example, the following declarations: int * numptr int num; numptr = # first declares a pointer variable called numptr that will be used to point to data of type int. the second declaration declares a normal variable and is put there for comparison. the third line assigns the address of the num variable to the numptr pointer. the address of any variable can be obtained by using the address operator, &, as is used in this example. bear in mind that once assigned, the numptr pointer contains the address of the num variable, not the value of its data. the above example could also be rewritten such that the pointer is straightaway initialized with an address when it is first declared: int num; int * numptr = # in order to further illustrate the difference between normal variables and pointer variables, consider the following, which is not a full c program but simply a fragment to illustrate our point: int num = 7; int * numptr = # printf ("%d\n", num); printf ("%d\n", numptr); printf ("%d\n", &num); printf ("%d\n", *numptr); 161
the first line declare a normal variable, num, which is initialized to contain the data 7. next, a pointer variable, numptr, is declared, which is initialized to point to the address of num. the next four lines use the printf( ) function, which causes some data to be printed to some display terminal connected to the serial port. the first such line displays the contents of the num variable, which is in this case the value 7. the next displays the contents of the numptr pointer, which is really some weird-looking number that is the address of the num variable. the third such line also displays the addresss of the num variable because the address operator is used to obtain num's address. the last line displays the actual data to which the numptr pointer is pointing, which is 7. the * symbol is called the indirection operator, and when used with a pointer, indirectly obtains the data whose address is pointed to by the pointer. therefore, the output display on the terminal would show: 7 13452 (or some other weird-looking number) 13452 (or some other weird-looking number) 7 a pointer's memory type recall that pointers are also variables, so the question arises where they should be stored. when declaring pointers, we can specify different types of memory areas that these pointers should be in, for example: int * xdata numptr = & num; this is the same as our previous pointer examples. we declare a pointer numptr, which points to data of type int stored in the num variable. the difference here is the use of the memory type specifier xdata after the *. this is specifies that pointer numptr should reside in external data memory ( xdata ), and we say that the pointer's memory type is xdata . typed pointers we can go even further when declaring pointers. consider the example: int data * xdata numptr = # the above statement declares the same pointer numptr to reside in external data memory ( xdata ), and this pointer points to data of type int that is itself stored in the variable num in internal data memory ( data ). the memory type specifier, data , before the * specifies the data memory type while the memory type specifier, xdata , after the * specifies the pointer memory type. pointer declarations where the data memory types are explicitly specified are called typed pointers. typed pointers have the property that you specify in your code where the data pointed by pointers should reside. the size of typed pointers depends on the data memory type and could be one or two bytes. untyped pointers when we do not explicitly state the data memory type when declaring pointers, we get untyped pointers, which are generic pointers that can point to data residing in any type of memory. untyped pointers have the advantage that they can be used to point to any data independent of the type of memory in which the data is stored. all untyped pointers consist of 3 bytes, and are hence larger than typed pointers. untyped pointers are also generally slower because the data memory type is not determined or known until the complied program is run at runtime. the first byte of untyped pointers refers to the data memory type, which is simply a number according to the following table. the second and third bytes are,respectively,the higher-order and lower-order bytes of the address being pointed to. an untyped pointer is declared just like normal c, where: int * xdata numptr = # does not explicitly specify the memory type of the data pointed to by the pointer. in this case, we are using untyped pointers. 162
data memory type values stored in first byte of untyped pointers value data memory type 1 idata 2 xdata 3 pdata 4 data/bdata 5 code functions in programming the 8051 in assembly, we learnt the advantages of using subroutines to group together common and frequently used instructions. the same concept appears in 8051 c, but instead of calling them subroutines, we call them functions . as in conventional c, a function must be declared and defined. a function definition includes a list of the number and types of inputs, and the type of the output (return type), puls a description of the internal contents, or what is to be done within that function. the format of a typical function definition is as follows: return_type function_name (arguments) [memory] [reentrant] [interrupt] [using] { ? } where return_type refers to the data type of the return (output) value function_name is any name that you wish to call the function as arguments is the list of the type and number of input (argument) values memory refers to an explicit memory model (small, compact or large) reentrant refers to whether the function is reentrant (recursive) interrupt indicates that the function is acctually an isr using explicitly specifies which register bank to use consider a typical example, a function to calculate the sum of two numbers: int sum (int a, int b) { return a + b; } this function is called sum and takes in two arguments, both of type int. the return type is also int, meaning that the output (return value) would be an int. within the body of the function, delimited by braces, we see that the return value is basically the sum of the two agruments. in our example above, we omitted explicitly specifying the options: memory, reentrant, interrupt, and using. this means that the arguments passed to the function would be using the default small memory model, meaning that they would be stored in internal data memory. this function is also by default non-recursive and a normal function, not an isr. meanwhile, the default register bank is bank 0. parameter passing in 8051 c, parameters are passed to and from functions and used as function arguments (inputs). nevertheless, the technical details of where and how these parameters are stored are transparent to the programmer, who does not need to worry about these techinalities. in 8051 c, parameters are passed through the register or through memory. passing parameters through registers is faster and is the default way in which things are done. the registers used and their purpose are described in more detail below. 163
registers used in parameter passing number of argument char / 1-byte pointer int / 2-byte pointer long/float generic pointer 1 r7 r6 & r7 r4?r7 r1?r3 2 r5 r4 &r5 r4?r7 3 r3 r2 & r3 since there are only eight registers in the 8051, there may be situations where we do not have enough regist- ers for parameter passing. when this happens, the remaining parameters can be passed through fixed memory loacations. to specify that all parameters will be passed via memory, the noregparms control directive is used. to specify the reverse, use the regparms control directive. return values unlike parameters, which can be passed by using either registers or memory locations, output values must be returned from functions via registers. the following table shows the registers used in returning different types of values from functions. registers used in returning values from functions return type register description bit carry flag (c) char/unsigned char/1-byte pointer r7 int/unsigned int/2-byte pointer r6 & r7 msb in r6, lsb in r7 long/unsigned long r4?r7 msb in r4, lsb in r7 float r4?r7 32-bit ieee format generic pointer r1?r3 memory type in r3, msb in r2, lsb in r1 164
appendix c: stc89xx series selection table type 12t/6t 8051 mcu operating voltage (v) f l a s h (b) s a r m (b) t i m e r u a r t d p t r pca/ pwm d/a a/ d w d t e e p r o m (b) internal low voltage interrupt internal reset threshold voltage can be configured external interrupts which can wake up power down mode special timer for waking power down mode package of 40-pin (35 i/o ports) package of 44-pin (39 i/o ports) stc89c51rc 5.5~3.3 4k 512 3 1 2 n n y 4k y n 4 n pdip lqfp/ plcc stc89c52rc 5.5~3.3 8k 512 3 1 2 n n y 4k y n 4 n pdip lqfp/ plcc stc89c53rc 5.5~3.3 13k 512 3 1 2 n n y / y n 4 n pdip lqfp/ plcc stc89le51rc 3.6~2.0 4k 512 3 1 2 n n y 4k y n 4 n pdip lqfp/ plcc stc89le52rc 3.6~2.0 8k 512 3 1 2 n n y 4k y n 4 n pdip lqfp/ plcc stc89le53rc 3.6~2.0 13k 512 3 1 2 n n y / y n 4 n pdip lqfp/ plcc stc89c54rd+ 5.5~3.3 16k 1280 3 1 2 n n y 45k y n 4 n pdip lqfp/ plcc stc89c58rd+ 5.5~3.3 32k 1280 3 1 2 n n y 29k y n 4 n pdip lqfp/ plcc stc89c516rd+ 5.5~3.3 61k 1280 3 1 2 n n y / y n 4 n pdip lqfp/ plcc STC89LE54RD+ 3.6~2.0 16k 1280 3 1 2 n n y 45k y n 4 n pdip lqfp/ plcc stc89le58rd+ 3.6~2.0 32k 1280 3 1 2 n n y 29k y n 4 n pdip lqfp/ plcc stc89le516rd+ 3.6~2.0 61k 1280 3 1 2 n n y / y n 4 n pdip lqfp/ plcc 165

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